Improving Lifetime And Performance Of SSD By Exploiting Inherent Heterogeneous And Parallelism

SSDs(Solid-State Drives)are emerging to become the major storage devices in computer systems because of their better read/write performance compared to HDDs(Hard Disk Drives).To increase the storage density(Gib/mm~2)of flash chips,flash manufacturers are dedicating on developing multi level cells and 3D stack technique.Multi level cell stores multiple data bits within one flash cell,increasing the storage capacity while flash cells are not increased.On the other hand,3D stack technique stacks flash cells vertically,greatly increasing the number of flash cells integrated within one chip.These techniques have great impact on increasing storage density of flash chips,however,they also bring some challenges on designing SSDs.The first challenge comes in the lifetime due to less P/E cycles can be endured by multi level cells.And the second challenge comes in the write performance due to longer write latency of multi level cells and the one-shot programming method introduced in 3D stacked flash.Therefore,improving SSD designs according to the characteristics of emerging flash techniques to finally improve lifetime and write performance is extraordinarily valuable.This thesis presents studies on SSD designs based on flash characteristics,and aims to improve SSD lifetime and performance.The contributions of this thesis are summarized as follows:Exploiting data-pattern heterogeneous of flash cells by bit-flipping schemes to improving lifetime of MLC flash.Multi level cells use multiple states for storing multiple bits within one cell.Especially,MLC(Multi-Level Cell)has four states,they correspond to”00”,”01”,”10”,and”11”,respectively,therefore,two bits can be stored within one cell.Existing studies revealed the facts that the four MLC states have significantly different impact on cell wear,retention error,and energy con-sumption.According to these observations,it is possible to manipulate the data to be programmed to reduce cell wear and retention error,finally improving the lifetime of MLC flash.This study explores bit-flipping schemes,discusses implementation of bit-flipping within SSD,and evaluates the benefits of various bit-flipping schemes on improving lifetime of MLC flash.Experiments manifest that intro-ducing bit-flipping schemes into SSD is able to decrease cell wear by up to 28%,and reduce retention error by up to 53%.Exploiting page-type heterogeneous by page-type aware allocation to improve write/read performance.TLC(Triple-Level Cell)flash has three types of pages,namely LSB,CSB,and MSB.These three types of page exhibit significantly different program latency.Especially,program latency of MSB is ten times longer than that of LSB.This study firstly reveals the fact that most user write requests would be served by the slowest MSB page when allocating pages without consideration of page types,finally leading to degraded performance.Accordingly,this study presents a page-type aware SSD design,named PA-SSD.The core idea of PA-SSD is allocating pages with the same type for sub-requests of any given user write request,to mitigate the imbalanced program latency among them.Specifically,PA-SSD specifies page-types for user write requests,and then allocates pages for sub-requests according to their specified page-types.Evaluation is done on popular SSD simulator,and the results show that PA-SSD improves write performance by 2.4 times and improves read performance by 1.5 time.Exploiting page-type heterogeneous by page-type aware transaction scheduling policy to re-duce write response time.Upon the arrival of user write requests to host interface of SSD,they are segmented into page-sized transactions(also known as sub-requests),which are then scheduled by TSU(Transaction Scheduling Unit)after their PPN(Physical Page Number)are determined.For a TLC SSD,the transactions would be allocated with pages in different types.This study analyzes the impact of transactions'page-types on write response time,and points out the opportunity to reduce write response time by scheduling transactions according to their page-types.Accordingly,this study presents PATS,a page-type aware transaction scheduling policy,to prioritize transactions with LSB pages over other write transactions,finally reducing overall write response time.Besides,some mech-anisms are designed in PATS to avoid transactions allocated with CSB pages and MSB pages becoming starved.PATS is implemented based on PA-SSD.Evaluation results show that write response time can be reduced by 30%when PATS is utilized.Exploiting flash type heterogeneous and parallelism in hybrid SSD to improve write per-formance.Due to the unsatisfactory write performance of TLC flash,researchers pay attention on designing hybrid SSD that using both SLC and TLC flash,in which SLC flash is used as write buffer zone,to achieve both high performance and storage capacity.Upon studies on one-shot programming method of 3D-stacked TLC,flash layout,page allocation strategy,and data migration policy in SLC-TLC combined hybrid SSD,this study presents SPA-SSD(SLC and Parallelism Aware hybrid SSD).Two major techniques are introduced in SPA-SSD,they are TPJ-PA(Type-Parallelism Joint Page Al-location)and QPC-DM(Queue-length and Parallelism Constrained Data Migration).The TPJ-PA allocates pages for write transactions according to not only SLC capacity but also parallelism to maxi-mize resource utilization within hybrid SSD.The QPC-DM triggers data migration without degrading user write performance by analyzing the device queue length and available flash resources.To evaluate performance of SLC-TLC combined hybrid SSD,a novel simulator HybridSim is developed based on MQSim.Experimental results on HybridSim show that TPJ-PA improves write throughput by 60%,while QPC-DM improves write throughput by up to 10 times.