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40nm Nickel Silicide Process Development

Posted on:2015-12-02Degree:MasterType:Thesis
Country:ChinaCandidate:C F WangFull Text:PDF
GTID:2308330464963448Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
40nm technology is still domestically an advanced process, although its mass production has been internationally achieved. In the development of 40nm process platform, a series of research has been conducted focusing on the Ni silicide process integration, development and optimization. The major achievements are:1. We successfully developed a 40nm process which integrated Ni silicide process. There are five main steps:1) Pre-cleaning and removal of SAB residual oxide; 2) NiPt/TiN deposition; 3) RTA1; 4) Removal of TiN layer and NiPt residue; 5) RTA2. The thickness, resistance and leakage measurement results show that the Ni silicide process meet the basic requirement.2. Minimizing NiSi defects:NiSi defect can be detected through EBEAM scan on SRAM region. The reason why NMOS defect issue is more serious than that of PMOS is analyzed. A series of experiments were conducted and the experimental results demonstrated that the quantity of NiSi defects can be improved through 1) Optimizing source/drain anneal spike temperature; 2) Reducing SMT stress; 3) Increasing Pt concentration in NiPt; 4) PAI process before NiPt deposition; 5) Increasing TiN cap thickness on NiPt.3. Ni-Silicide process for source/drain embedded SiGe:Depositing silicon cap layer on SiGe can result in a stable NiSi compound, avoiding the technical problems of Ni-Ge-silicide. However, it was discovered that silicon CAP layer thickness, and PAI implant have a very big impact on the formation of NiSi. Process optimization is still necessary.
Keywords/Search Tags:Nickel silicide, Nisi defect, Source/Drain embedded SiGe
PDF Full Text Request
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