| With the development of Moore’s law,the size of the device is rapidly scaling down.However,the supply voltage(FDD)of metal-oxide-semiconductor field-effect transistor(MOSFET)cannot be scaled down with the same ratio due to the Boltzmann tyranny.In recent decades,the VDD has been maintained within the range of 0.7V～1V.Thus,the power dissipation has become a big issue for the development of Integrated Circuit(IC).To solve the power consumption problem,the device with high on-state current to off-state current ratio(ION/IOFF)and steep subthreshold swing(SS)are needed to make sure that the VDD of the device can be reduced while maintain the low IOFF since the power consists of two parts:static power and dynamic power.Hence,in this dissertation,the promising low power devices including Tunneling Field-Effect Transistor(TFET),Piezoelectric Field-Effect Transistor(Piezo-FET)and Negative-Capacitance Field-Effect Transistor(NC-FET)are theoretically investigated.The main contents and the corresponding results are listed below.Firstly,based on the lattice-matched GeSn/SiGeSn that forming type-Ⅱ staggered heterojunction,the performance of GeSn/SiGeSn hetero-TFET with conventional device structure and the back-gate biasing effect is investigated.The results show that the N-type and P-type GeSn/SiGeSn hetero-TFET depict the symmetric performance that can be used to achieve complementary TFET(CTFET).And,the improved performance of hetero-TFET as compared with the corresponding GeSn homo device is mainly owing to the higher carrier density nearby the tunneling junction due to the presence of type-Ⅱ heterojunction.Considering the back-gate biasing(Fbs)effect,the results show that the onset voltage(VONSET)of the hetero-TFET demonstrates the negative shift with the increased VBS.And the hetero-TFET with VBS<0 demonstrates superior SS and ION/IOFF characteristics as compared with the device with VBS≥0.Secondly,the GeSn/SiGeSn hetero line-TFET(HL-TFET)is designed by combining the line tunneling together with the type-Ⅱ hetero tunneling junction.Ge0.92Sn0.08/Si0.47Ge0.33Sn0.20 HL-TFET achieves 6.7 times and 1.2 times higher ION as compared with Ge0.92Sn0.08/Si0.47Ge0.33Sn0.20 hetero-TFET and Ge0.92Sn0.08 homo line-TFET,respectively.Meanwhile,the average SS in Ge0.92Sn0.08/Si0.47Ge0.33Sn0.20 HL-TFET is 46.8mV/decade which is 8mV/decade and 3mV/decade smaller in comparison with Ge0.92Sn0.08/Si0.47Ge0.33Sn0.20 hetero-TFET and Ge0.92Sn0.08 homo line-TFET,respectively.The improved performance in HL-TFET is due to the fact that the almost all the carrier density with high value are located in the pocket region attributing to the higher line tunneling probability.And,the ION of HL-TFET increases with the Sn composition of GeSn increases is owing to the reduced tunneling barrier.Thirdly,the strain engineering of GeSn FinTFET is investigated.The strain components for 1GPa uniaxial tensile stress along different directions in(001)plane are calculated.Then,the band structure of the 1GPa uniaxially tensile stressed Ge0.90Sn0.10 is calculated using k·p theory.The bandgap of Ge0.90Sn0.10 is reduced under the uniaxial tensile stress and the impact of direction of stress on bandgap is negligible.The reduced tunneling mass(mr)that perpendicular to the stress direction is decreased while the mr along the direction of stress is increased and the mr shows significant stress direction dependence.Under |VDD|=0.3V,1GPa uniaxially tensile stressed Ge0.9OSn0.10 FinTFET with Fin along[100]direction,the ION of N-type and P-type Point-FinTFET is increased 7.6%and 11.7%,respectively,as compared with the relaxed Ge0.90Sn0.10 Point-FinTFET.While,under |VDD|=0.3V,1GPa uniaxially tensile stressed Ge0.90Sn0.10 FinTFET with Fin along[110]direction,the ION of N-type and P-type Line-FinTFET is increased 99.3%、96.7%,respectively,as compared with the relaxed Ge0.90Sn0.10 FinTFET.Fourthly,the theoretical investigation of Piezo-FinFET is carried out.The device structure of Piezo-FinFET is designed.The analytical expression of stress and strain in Piezo-FinFET is calculated and the SS of the ultra-thin-boday(UTB)FinFET is analytical modeled.For the Peizo-FinFET,the SS is mainly related to the change of electron affinity of channel semiconductor(χSCT)with gate voltage(VG).And,the change of electron affinity is related to the conduction band edge shift(△Ec)that is △χSCT=-△Ec.The maximum |△Ec| is obtained when the direction of strain is aligned with the longitude direction of valley.And,Si Piezo-FinFET achieves SS of 42mV/decade with Fin width direction along[001],while for Ge Piezo-FinFET with Fin width along[111]direction,the steep SS of 40mV/decade is obtained.The results also show that,with the increament of the width of piezo-layer(WPic)and the width of Fin(Wfin),the |△Ec| reduces leading to larger SS.Considering the property of the piezo-material PZT-5H used in this work,for Si Piezo-FinFET with fin width along[001]direction,the lowest boundary of SS is 35mV/decade.Fifthly,the theoretical investigation of NC-FET is carried out.Considering the different factors that affect the capacitance of gate insulator(Cins)which is the result of the capacitance of ferroelectric layer(CFE)in series with the capacitance of oxide layer(COX).Analyzing the impact of different factors on the NC-FET with Cins>O and Cins<O,respectively.And,investigating the impact of temperature(T),thickness of ferroelectric layer(tFE)and the thickness of oxide layer(tOX)on the NC-FET with Cins>0.The result shows that the critical values for T、tFE、tOX exist in which the Cins=0 and Cins is quite sensitive to these three parameters.T、tFE、tox can be adjusted to achieve a targeted gate voltage gain(GOX,T)and the adjusting range of parameters is larger when GOX,T gets smaller For NC-FET with Cins>O,the SS cannot be smaller than 60mV/decade.But,as compared with the traditional MOSFET device,the NC-FET with Cins>0 is an promising device for low power application owing to the increased transconductance due to the negative CFE<0.For NC-FET with Cins>O,the SS gets steeper and IDS increase with tFE increases and the sensitivity to tFE gets weaker.With tOX and T increases,the IDS of NC-FET decreases and the sensitivity to tOX and T gets weaker.And the result also shows that,by adjusting tFE and choosing the ferroelectric material,the behavior of threshold voltage shifting with the increased temperature can be improved. |
