Novel Iterative Signal Detection Algorithm And VLSI Implementation

With the development of information technology,especially for the mobile Internet,there is an increasing demand for high-speed data transmission centered on multimedia services.At the same time,the development and application of new technologies such as intelligent transportation,intelligent production,and smart medical treatment have made many traditional industries face a comprehensive information upgrade.As an important fundamentalal technology of the modern information technology,wireless communica-tion will play a more important role in the future,which would not only support the con-nection between people,but also provide wireless access for a huge number of machines and devices.Thus higher data rates,lower latency,higher reliability,and massive access capacity would be required.In contrast,the VLSI design and implementation of digital signal processing in modern wireless communication system is facing the challenges of processing speed,delay,and power consumption caused by the increasingly difficulty of CMOS technology upgrade.As representative technology of modern wireless commu-nication baseband processing,iterative detection provides near-shannon capacity perfor-mance while cost high hardware complexity for VLSI implementation.Therefore,the iterative signal detection method and its high-performance,low-complexity,low-power VLSI implementation have become an important research hotspot.In this paper,the iterative signal detection and its implementation technology in the baseband signal processing of future wireless communication systems are the main re-search objects.Aiming at high performance,low complexity and high efficiency,a bit-wise iterative detection based on stochastic computing is proposed,including key arith-metic units,SCMA detectors,channel code decoders,and joint iterative detection and decoding methods.The main innovations of this paper are as follows:1.In order to solve the problems of high computational complexity,slow conver-gence and correlation decreasing between bit streams for the stochastic computing based communication signal processing,a low complexity random bit stream generation method,shared random number generator and fast convergence stochastic normalization unit are proposed.·The low complexity random bit stream generation method can directly convert the Euclidean distance,log likelihood ratio and other variables,which is quite com-monly used in communciation baseband signal processing,into the random bit streams.Benefiting from the convenient calculation and simple structure,the hardware con-sumption is reduced by 10 times compared with the traditional method.· The shared random number generator solves the problem of random number sharing in the stochastic computing based DSP system,which greatly reduces the hardware overhead of the random number generators.·The fast convergence stochastic normalization unit mainly solves the problems of"hold-state" and "overflow" of the traditional stochastic normalization method,resulting in three times faster convergence compared with the traditional stochastic normalization method.In the low calculation accuracy application,the hardware ef-ficiency is 1.5 times higher with respect to the traditional binary calculation method.2.As a kind of non-orthogonal multiple access technologies,SCMA has received ex-tensive attention due to its strong access capability,simple receiving algorithm and high compatibility with existing systems.However,its best detection algorithm,Message Pass-ing Algorithm is difficult to implement in hardware due to various nonlinear operations,making it difficult to apply in practical systems.At present,the main application algorithm is the Max-Log MPA algorithm based on logarithmic domain approximation.However,Max-Log MPA algorithm still has problems such as poor detection performance,high hardware implementation complexity,and long critical path.Therefore,this thesis de-signs a stochastic bit-wise iterative SCMA detection method based on the proposed key stochastic computing calculation unit.The detection performance can approach the MPA algorithm with only 1/15 hardware cost of Max-Log MPA.The hardware efficiency is three times that of Max-Log MPA.3.As the first channel coding scheme that can be theoretically proved to reach Shan-non's limit,Polar code has attracted the attention of researchers and industry and also has been accepted by 3GPP organization as the control channel coding scheme for future 5G systems.One of the main factors limiting the application of Polar in future data channel transmission is the decoding delay bottleneck caused by the serial decoding characteris-tics of the best decoding SCL algorithm.At the same time,the soft decoding output of the SCL algorithm is also difficult.Another type of decoding algorithm for Polar code is BP.Its natural parallel decoding structure and soft input soft output characteristics make it an important candidate for the Polar decoding scheme.However,its iterative process complexity leads to high hardware cost and data access difficulties.At present,stream-wise iterative s.tochastic computing based Polar decoder has been proposed,which exhibits extremely low hardware cost,hut still has a problem of low message passing efficienc and slow convergence.In this paper,a bit-wise iterative stochas'tic computing based Polar coder is designed,and a series of complexity and convergence speed optimization methods are proposed.The proposed bit-wise iterative stochastic Polar decoder maintains compa-rable decoding performance,with 19 times decoding latency reduction and achieves twice the hardware efficiency gain.4.The iterative detection and decoding scheme(IDD)based on Turbo-like structure has attracted much attention due to its excellent BER performance.However,its iterative detection and decoding structure with outer-loophas lower information passing efficiency and slower convergence.In this paper,SCMA detection and LDPC decoding are repre-sented in the same factor graph,A joint detection and decoding algorithms are proposed to achieve better bit error rate performance than IDD scheme,and also:achieve faster con-vergence.On this basis,this paper also propose,s a VLSI implementation scheme for joint detection and decoding scheme based on.stochastic computing.The results show that the stochastic joint detection and decoder scheme outperforms existing schemes on bit error rate performance.The hardware cost is reduced by a 10 times and the hardware efficiency is increased by 2 times.