Algorithm Optimization And Hardware Implementation Of New Multiple Access Technique SCMA

Multiple access technique is one of the leading factor to support modern communication technology,which emphasizes its significance in the evolution of the communication.The next generation communication technology 5G proposes the new indexes of large-scale connection and “Gbps” throughput,which challenges the traditional multiple access techniques.To handle such bottleneck,Non-orthogonal multiple access(NOMA)techniques are proposed.And among these,successive interference cancellation based NOMA,pattern division multiple access(PDMA),Turbo based interleaving division multiple access,and LDPC based sparse code multiple access(SCMA)are the most promising candidates for 5G.Compared to other non-orthogonal multiple access techniques,SCMA enjoys the properties of lower complexity and better compatibility because of the multiple user decoding(MUD)scheme,and that is what makes it stand out.To introduce SCMA into practical systems,there still remains several problems to be settled: the algorithm simplification and the highefficiency hardware architecture.In this paper,we make series optimization towards the original algorithm and the hardware implementation for SCMA.For algorithm optimization,we mainly focused on the section of transmission,detection and codebook design.1)For the transmitter,we propose the interleaving superposition transmitting scheme and patternbased two-dimensional transmitting scheme.Sparse code multiple access technique compress the users' information into several codeword,and transmit them through independent sub-carriers of orthogonal frequency division multiplexing(OFDM),which means users' s information of the same sub-carrier will be interfered by the same noise while transmitting and thus influence the performance at the detector.Interleaving superposition scheme introduced the controlled-randomness into the procedure of compressing,which makes the information of the same user will appear on different sub-carriers and thus can be recovered through centrallimit theorem.Apart from this,we also proposed the two-dimensional transmitting scheme,which makes the one-dimensional SCMA signals into two-dimensional patterns.Second order partial differential operator based image-inpainting techniques and convolutional neural network based image-training techniques are introduced in the design,which lower the dependency of channel estimation and improve the accuracy of decoding.2)For the detector,we propose series approximation and simplification towards the original message passing algorithm(MPA)to make it more friendly for the hardware implementation with negligible performance loss.The details of these optimization includes stochastic computation,Log-domain approximation,first and second order module value approximation of the initial conditional probability,and pruned-tree scheme.All of these manners reduce the complexity massively.Beside of this,joint detection and decoding(JDD)of polar-coded SCMA systems are also considered in this paper,which further lowers the complexity of the systems.3)For the codebook design of large-scale SCMA sytem,we also make great efforts towards the complexity reduction.The details include the quasi-cyclic design of generation matrix,and the rotationbased mother constellation operators.Compared to the conventional codebook design schemes,this method avoid the multiplication of complex value,constellation mapping,and shuffling,which reduces the design complexity significantly.It support the realization of large-scale multiple access technique with bearable performance loss.For hardware implementation,we propose the common architecture of SCMA detectors,and make corresponding adjustment according to the algorithm optimizations discussed above,which can adapt to different application scenarios.The common detectors can be distinguished as deterministic-domain detector,stochastic-domain detector,and image-domain detector according to different algorithms.1)Deterministicdomain detector utilizes very large scale integration(VLSI)design techniques to analyze the corresponding timing and loops of the architecture.For timing optimization,stage-based architecture is proposed to replaced the original step-based one,which improve the throughput massively when pipeline technique is introduced.Meanwhile,the shortest loop of the architecture is acquired through the loop analysis,which can help to determine the highest clock frequency and the folding factor of the folding design technique.Based on this folding factor,we introduce the “step-based folding” into our architecture,which can significantly improve the hardware efficiency.We also apply the initial probability simplification,Log-domain approximation,and pruned-tree algorithm into the architecture to further reduce its hardware consumption and satisfy the practical systems.2)Stochastic-domain detector is the approximation of message passing algorithm,which utilize the bit stream of 0 and 1 to represent the propagated conditional probability.These bit streams are then processed by the basic gates at the detector.The processing procedure is extremely convenient in that the single bit only needs to be calculated through AND,OR and INV gates,which intensively simplifies the architecture of the detector,and can be used in some special scenarios such as the power-limited situation.Also,the calculating accuracy can be controlled through the adjustment of the length of the streams.3)Two-dimensional image-domain detector is based on the pattern construction of SCMA signals,and the main parts of this detector includes the two-dimensional mapping unit,the convolutional neural network and the total-variation pre-filter.The parameters of the network can be achieved through the image training procedure,and then the parameters are used to adjust the basic units of the architecture.The total-variation pre-filter is applied to reduce the random noise before the final decoding to improve the error rate performance,which uses the semi-pixel difference manner to realize the maximum gradient denoising.In this paper,we also compare the different common detectors about their application scenarios and their advantages and disadvantages.All the detectors discussed above are implemented through application specific integrated circuit(ASIC)with the c omplementary metal oxide semiconductor(CMOS)45nm technology.We analyze the effectiveness of these architecture based on the area of the hardware,the highest throughput,the longest latency,the highest clock frequency,and the lowest power consumption according to the parameters provided by ASIC.