Research On Reliability Mechanisms And Models For Silicon Carbide Based Power MOSFETs

Silicon carbide based power metal-oxide-semiconductor field-effect transistor（SiC power MOSFET）is regarded as one of the most promising power devices for the advantages of high breakdown voltage,high conduction current,fast switching speed,low power losses and fine thermal stability.However,the severe application environments with high temperature,high voltage and high current make SiC power MOSFETs be faced with serious reliability challenges.Therefore,there are strong requirements on investigating the reliability mechanisms of SiC power MOSFETs and modeling their degradations.It is of great significance for improving the performances of SiC power MOSFETs and predicting their lifetimes in power systems.A novel interfacial damage extraction method is proposed.Based on this method,the degradation mechanisms for SiC power MOSFETs under different realistic stress environments including dynamic gate stress,unclamped-inductive switching（UIS）stress,short-circuit（SC）stress and repetitive switching stress are investigated in details.The concerned degradation characterization models are also established.The main creative results of this work are listed as follows.（1）An novel interfacial damage extraction method based on the stepwise capacitance versus voltage（C-V）curve of the device,which is suitable for SiC power MOSFETs,is proposed.The degradation of the interface above the channel region can be characterized by the shift of part II of the C-V curve while the degradation of the interface above the JFET region can be characterized by the shifts of part III and IV.According to these characteristics,the locations,the types and the densities of the charges injected into the gate oxide interface of the device can be extracted.（2）The degradation mechanisms of SiC power MOSFETs during the high-voltage stage and the zero-voltage stage of the dynamic gate stress procedure are verified,which are the injection of charges into the whole gate oxide interface and the release of these charges,respectively.They separately result in the shift of threshold voltage(V_th)and the recovery of it.The V_th degradation characterization model for SiC power MOSFETs under dynamic gate stress is also established.The error of this model is lower than 4%.（3）The main degradation mechanism of SiC power MOSFETs under repetitive UIS stress is demonstrated to be the injection of positive charges into the gate oxide interface above the JFET region during the avalanche process.It rarely influences the static electric parameters of the device,but enlarges the gate-drain capacitance(C_gd).The switching times of SiC power MOSFETs,especially the turn-OFF times,are then increased.The degradation characterization model of the C_gd versus the avalanche stress time is established,whose error is lower than 1%.（4）The injection of negative charges into the gate oxide interface above the channel region is proved to be the dominant degradation mechanism of SiC power MOSFETs under repetitive SC stress.Therefore,with the increase of stress cycles,the V_th shifts to the positive direction.The increasing V_th furtherly lifts the Miller plateau voltage(V_gp),leading to the delay of turn-ON times and the drop of turn-OFF times.Moreover,an improved device structure with a step P-body,which is of high SC reliability,is proposed.This novel structure can suppress the degradations of SiC power MOSFETs under SC stress by decreasing the impact ionization rate（I.I.）along the oxide interface above the channel region by 33.8%.（5）The degradation mechanism of SiC power MOSFETs under repetitive switching stress is demonstrated to be the injection of negative charges into the gate oxide interface along the channel region during the conduction stage.It leads to the rise of the V_th.Furthermore,the investigation indicates that the turn-ON process of the device,which rarely leads to the injection of charges directly,rises the junction temperature,contributing to the injection of negative charges into the gate oxide above the channel during the conduction stage.