High Performance Network On Chip Design:Routing Algorithm And Energy Optimization

With the progress of information technology,tens of thousands processing elements are integrated on a single chip,and high-performance computer architectures have evolved into on-chip multiprocessor platforms.Hundreds of cores are connected together,and the intercon-necting problem becomes critically important.The Network-on-Chip(NoC)has been proposed as an efficient solution to handle this distinctive challenge by providing efficient and scalable communication infrastructures among the on-chip resources.With high-integration,low power consumption,low cost and small size,NoC meets the needs of various electronic products,and has gradually become the mainstream of ultra-large scale integrated circuit design.In this thesis,we focus on the high-performance Network-on-Chip(NoC)design and make efforts to conduct research on three major aspects:time optimization of network delay based on deadlock avoidance,energy optimization of voltage island distribution system based on data retransmission,and optimization of energy consumption based on network coding.In the aspect of networking delay optimization,this thesis proposes a new routing mechanism,which builds an analytical model of networking delay,using the queuing theory,under the condition of on-chip network wormhole switching,and the correctness is proved by the simulator.This thesis also designs a deadlock-free routing algorithm,which is based on branch-and bound algorithm,thereby guaranteeing deadlock freedom and minimizing the overall average networking delay.Compared with the existing adaptive deadlock free algorithms,the simulation results show that the proposed algorithm has better performance in terms of throughput and latency.In the aspect of voltage island distribution energy consumption,a new energy consumption model is proposed for the voltage island allocation considering the influence of supply voltage on the data transmission error rate.The proposed algorithm is based on voltage island division,IP core mapping and routing path selection.In the voltage island division problem,not only the computational energy consumption of the IP core is considered,but also the communication energy consumption of the data between the IP cores under retransmission is considered;the IP core mapping algorithm takes the voltage island problem into consideration for IP core mapping;The routing algorithm is designed in the case of data retransmission.The experimental results show that the design method can effectively reduce the system energy consumption.In the aspect of network coding energy optimization,this thesis studies the coding/decoding algorithm of NoC system.At the encoding end,the concatenated convolutional code is designed.As the coding scheme of NoC node,a new fault-tolerant forwarding protocol is proposed,which is combined with network coding algorithm for reducing the forwarding number.At the decod-ing end,a joint decoding algorithm using correlation between multiple signals is proposed.The simulation results show that the proposed scheme can significantly reduce the energy consump-tion.Under the same requirements of service quality,the coding gain reaches 6 dB,and the full diversity order can be obtained on the fading channel.