Research On Key Technologies Of The HDL Code Quality Evaluation And Optimization Of The Circuits Performance

As an important part in SoC/ASIC chip quality assurance system, the criteria andcontrol of HDL source code quality has become a key factor to the quality andcredibility control of SoC/ASIC chip. In order to address the challenges facing us in thepresent SoC/ASIC design, it is urgent to propose a novel method to evaluate the HDLsource code quality to realize the targets, such as finishing the development ofhigh-quality HDL source code in a rapid and highly efficient manner and detectingflaws at an early stage of the chip design. In this paper, two critical techniques of theHDL source code evaluation are studied, which are the abstraction method of the HDLcode and the method of transforming cyclic circuits into acyclic equivalents.Furthermore, these methods are applied in the design of three VLSI designs which areXD_BUS, MQ-encoder and MMC/SD/TF card controller. The main studies andconclusive results are as follows.1. Since HDL source code is checked by fairness policy by available EDA toolsaccording to some specified rules, some rules independent defects cannot be laid specialstress on. In view of this fact, the paper proposed a complexity oriented abstractionmethod of the HDL code. Using this method, the HDL code is defined as a two-levelnetwork. And in this network, the weight of edges is used to describe the complexity ofnodes; and high complexity nodes have been chosen as the source-point of the network.Furthermore, based on this network, the Dijkstra method is introduced to search thehighest complexity parts of the source codes. It should be noted that four types of VLSIdesigns are selected in order to prove the universality of the proposed method, such asthe PE (a RISC CPU of XDNP), the XD_BUS (bus of XDNP,) MQ-encoder, andMMC/SD/TF card controller. Experiments show that this method is able to effectivelylocate the most complex part of HDL source codes. With the help of this method, thecode qualities of the proposed VLSI designs are improved. Moreover, some advices arepresented according to the analyses of these experimental results.2. Cyclic circuit is able to reduce the area and power consumption, but it is difficultto analyze by tools such as static timing analyzers. Furthermore, simulation and DFT forthe cyclic circuit are more expensive and complicated. Thus, in order to remove theunwanted cycles in the high-level synthesis process, a method for transforming cycliccircuits into acyclic equivalents based on the SAT is presented in this paper. Differentfrom the available researches, this paper uses the SAT and static logic implicationtechnique to represent the circuits. Meanwhile, by analyzing the structure and mechanism of the cyclic circuits, some novel rules are proposed to obtain the acyclicequivalents more precisely and effectively. Experiments were performed on theproposed VLSI designs and the IP cores which come from Opencore. Compared withthe available papers, the transforming time and the area of results are decreased,.3. In accordance with the quality evaluation results of the source codes and therequirements of the XDNP(Xidian network processor), this paper proposed a loosecoupling and split transaction On-Chip Bus which is called XD_BUS. Compared withthe common bus, each device is separated from the XD_BUS by introducingbuffer-devices, which leads that the devices connected with the bus can workindependently. Thus, this method decreases the coupling degree between the masterdevices and slave devices. Furthermore, split transaction mechanism is adopted in thedesign of the data-bus as follows: first, the data-receive channel and the data-transformchannel are separated; second, in each channel, every device has its own data-bus. As aresult, this scheme improves the concurrency ability of the XD_BUS. The proposedarchitecture is synthesized with SMIC0.18μm technology library. The implementationresult shows that the frequency of the proposed architecture is232MHz. Meanwhile, thethroughput of the XD_BUS is5.4Gbps@100MHz which is larger than the requirementsof the XDNP.4. Based on the quality evaluation results of the source codes, this paper hasproposed two VLSI designs for MQ-encoder, that is, Sequential MQ-encoder which iscapable of encoding one symbol per clock, and Two-context MQ-encoder which iscapable of encoding two symbols in parallel. Compared with available designs, thenovelties of these two architectures are as follows:(1) The correlations between thesequential pairs of context and its decision are analyzed. Moreover, the burst number ofCX and the burst number of the index value are studied. Due to these analyses, aconclusion is drawn in order to prevent the AE from stalling when the burst number ofthe context is larger than one.(2)The probabilities of different adjusting manners for theinterval register A and code register C before renormalization are given. On the basis ofthese data, a detector of leading-zero is proposed to simplify the renormalizationprocedure.(3) An improved mechanism has been proposed to acquire indexes byseparating the "start-up" states and remaining states. The proposed architectures aresynthesized with TSMC0.18μm HS technology library of ARM Company. Synthesisresult shows that the processing speed of the Two-context MQ-coder could reach ashigh as286.80MHz with a throughput of573.60Msymbols/sec. And the implementationresult shows that the throughput of the Sequential MQ-encoder is547Msymbols/sec with an area of79012.84μm2. Compared with the available designs, the throughput hasbeen increased.5. Generally, the method of hand-written RTL code has large number of defects,such as the inflexibility and low configurability. To remedy these defects, this paperproposed a reconfigurable design approach which can be used in the design of IP cores.By this method, the functions of IP cores are analyzed and then abstracted as theinstruction set. Meanwhile, the paper establishes a cell library which includescoarse-grained cells and fine-grained cells. Based on these files, we can complete thedesign of IP cores by scheduling different instructions. Finally, the MMC/SD/TF cardcontroller IP cores which are used in a radar digital signal processor are selected as theexperimental subjects. In this experiment, the characteristics of different card controllerIP cores are analyzed. And then, the conclusion is pointed out that the hardwarearchitectures of these IP cores are regular and similar. Based on this conclusion, usingthe proposed scheme, the design of the MMC/SD/TF card master controller IP core isrealized.