Study And Design On Hybrid SAR ADC

Successive approximation ADC has gradually become one of the main structureselection of low power consumption and high precision ADC because of the system structureadvantage. How to achieve low power consumption、high precision and low cost tradeoff inthe system structure optimization and the digital calibration algorithm research is one of thehotspots in the SAR ADC research.In this thesis, based on analysis of SAR ADC principle, a hybrid Res-Cap SAR ADC wasimplemented based on0.13m CMOS process. Then, in view of a detailed analysis of thePipelined SAR ADC, the clock logic in the system was resolved. A Cap-Res structure wasadopted in the second sub-SAR ADC to improve the performance. Digital adaptive filteralgorithms were proposed and simulated、validated in detail. At last, a Delta-Sigma ADC as areference ADC was designed for the implemtation of the above algorithms.The achievements and innovation points of this thesis are as follows:(1) A1.2V8-bit1Msps single-ended successive approximation register (SAR)analog-to-digital converter (ADC) was designed with a hybrid Res-Cap DAC, which wasintegrated with a ring oscillator and serial peripheral interface (SPI) for adjusting thesampling frequency according to the different system requirement. To resolve the problem ofthe noise and sampling frequency due to hybrid DAC, the f-3dB,DACand noise voltage wereused as a constraint for design. To satisfy the resolution of8-bit ADC, adding the feedbackcapacitor to pre-amplifier and increasing the area of the input transistors were adopted tominimize the offset voltage in the rail-to-rail comparator. The common voltage ofpre-amplifier was0.6V and the offset voltage was below2mV. The ring oscillator (OSC) wasproposed and designed with many inverters and single operational amplifier with adjustablecurrent for changeable sampling frequency. The chip was fabricated with0.13m CMOSprocess with an area of0.1mm2. The measurement results show that the differentialnonlinearity (DNL) and integral nonlinearity (INL) of the proposed ADC are+0.11/-0.18LSBand+0.8/-0.04LSB, respectively. The spurious free dynamic range (SFDR) andsignal-to-noise distortion ratio (SNDR) can get53dB and43.3dB, respectively. The FOMAof the design can reach7.7pJ·m/con. (2) A12-bit2Msps Pipelined SAR ADC was studied and designed. The two sub-SARADCs are connected with multiplying digital-to-analog converter (MDAC) in the PipelinedSAR ADC system. To satisfy the sampling and amplifying accuracy, the clock logic wasoptimized. The sampling phase of four clock periods and amplifying phase of four clockperiods were proposed. The relationship of the non-overlapping clock in pipeline ADC andsampling clock, SAR clock and reset clock in SAR ADC were resolved. The first stage sub-SAR ADC in Pipelined SAR ADC was designed with capacitor structure and the second submodules of7-bit SAR ADC were designed with hybrid capacitor-resistor structure andcapacitor structure, respectively. The simulated results shows that the Pipelined SAR ADCwith hybrid Res-Cap structure can obtain the ENOB of10.5bit and SNDR of65.0dB, andthe Pipelined SAR ADC with capacitor structure can obtain the ENOB of10.33bit and SNDRof63.9dB.(3) For improving the accuracy of ADC further, the digital adaptive filtering algorithmswere studiedincluding least mean square (LMS) algorithm, variable-step-size LMS algorithmand recursive least square (RLS) algorithm. In LMS algorithm, to minimize the processingproblem, the first bit in step size was proposed as the location of the decimal point. When itcomes to step multiplication, the truncated result was performed as actual product for nextoperation to solve convergence problem. The validation result by FPGA shows that the SNRof non-ideal ADC can be improved from61.37dB to64.29dB and SFDR can be improvedfrom80.68dB to83.65dB. In RLS algorithm, matrix multiplication and division operationswere involved, the algorithm parameter λ is decimal and arithmetic process will produce highprecision decimal, therefore the floating-point DSP algorithm hardware verification wasproposed. The validation result shows that the SNR of non-ideal ADC can be improved from11.31dB to20.88dB. The modeling of using has been done detailed. The Simulinksimulation results show that the variable-step-size LMS algorithm can double the convergencerate with the similar calibration accuracy compared with the LMS algorithm.(4) A1.25MHz16-bit Delta-Sigma ADC with1.2V supply as a reference ADC fordigital adaptive filtering algorithm was designed with configurable DR to realize the highprecision converter. To obtain the configurable DR and lower the power, the mash2-2modulator with configurable order and digital filters with configurable OSR were proposed to resolve the instability of the high order modulator and changeable OSR. To analysis the effectof non ideal errors on the modulator, the behavioral model and simulation for modulator anddigital filters were proposed to solve the problem of the complex selection of gain parametersto obtain stable performance. The chip was fabricated with0.13m CMOS process. Themeasured results show that the DR can change from55dB to95dB, ENOB is14.07bit andFOM is162.The above results of this thesis can be as a technical reference for the design of lowpower consumption, high speed and high precision ADC and the utilization of digitalcalibration algorithm.