Breakdown Model And New Trench Structures Of SOI High Voltafe Devices

SOI (Silicon On Insulator) high voltage integrated circuit is widely applied andbecomes the important trend of the Power Integrated Circuit because of its advantagessuch as high speed, low leakage current, superior isolation and perfect irradiation.Conventional SOI LDMOS (Lateral Double-diffused MOSFET) is the key device inSOI high voltage integrated circuit. The trade-off between breakdown voltage andspecific on-resistance in the LDMOS limits its application in high power field.RESURF technology is the typical technology to increase the breakdown voltage andoptimize BV~Ronthe tradeoff relation. RESURF has experienced the development of SR(Single RESURF), DR (Double RESURF), TR (Triple RESURF) technology. However,up to now, the existing researches focus on the device surface electric field, thetheoretical analysis of the vertical electric field is still lacking. Meanwhile, theanalytical model of the bulk silicon TR LDMOS is too simple, not pointing out how thedepth, thickness and doping concentration of the P-buried layer affect the deviceperformance, and there is no report about SOI TR LDMOS structure and its analyticalmodel. On the other hand, the trench LDMOS structure is proposed to shorten thedevice lateral area so as to further reduce the specific on-resistance. However, there stilllacks of the theoretical analysis of the trench LDMOS, especially of how the width,depth and permittivity of the trench affect the electric field distributions, the breakdowncharacteristics and on-resistance of the device.In this thesis, addressed the breakdown voltage problem of SOI LDMOS, thebreakdown theory, device structures and breakdown analytical models are researched.Two new analytical models and a new device structure are presented. The breakdownmodel of high voltage SOI TR LDMOS is developed, based on which, the SOI and BulkSilicon RESURF criterion are unified. Meanwhile, the breakdown model of highvoltage SOI trench LDMOS is proposed. The universal design method is presented andthe experiments of the SOI Trench LDMOS are implemented. The model demonstratesthe influence of the depth, width and permittivity of the trench on the device’s electricperformance. Furthermore, the high voltage SOI LDMOS with a variable-k dielectric trench structure is proposed and the tradeoff between breakdown voltage and specificon-resistance is optimized compared with conventional trench SOI LDMOS.1. The breakdown model of high voltage SOI TR LDMOS is proposed.The breakdown model of high voltage SOI TR LDMOS is presented in this thesis，demonstrating the modulation effect of the P layer on the electric field of the device.The analytical expressions of the surface and vertical electric field are given. TheRESURF criterion and the expression of the vertical breakdown voltage are derivedfrom the optimal surface and vertical electric field conditions. The influences of thedepth, thickness and doping concentration of the P buried layer on the devicebreakdown characteristics and on-resistance are investigated. The optimal design isachieved with a thin P layer buried located in the middle of the drift region, from whichthe simplified SOI TR condition is obtained. The specific on-resistance of SOI TRLDMOS is reduced by50%compared with that of SR LDMOS at the same breakdownvoltage. Based upon the TR model, the breakdown model of high voltage SOI MR（Multi-RESURF）LDMOS is derived. The specific on-resistance of MR LDMOS canbe further decreased compared with that of the TR LDMOS at the price of sacrificingsome breakdown voltage. Based on the self-aligned silicon gate process, the150V SOITR LDMOS is experimentally obtained on3.5μm top silicon layer,1μm buried oxidelayer SOI material.2. The SOI and Bulk Silicon RESURF criterion are unified.The SOI and Bulk Silicon RESURF criterion are unified by extending the SOI TRbreakdown model to other LDMOSFETs, which consummates the RESURF theory. Thesurface and vertical electric field expressions of SOI SR、DR、TR LDMOS are obtained,from which the unified RESURF condition and vertical breakdown voltage expressionsof SOI LDMOS are derived. The unified RESURF criterion reveals the relation anddistinction between Bulk Silicon LDMOS and SOI LDMOS. It is employed to guide thedesign of lateral high voltage devices.3. The breakdown model of high voltage SOI trench LDMOS is proposed and theuniversal trench design method is presented.The trench folds the drift region in the vertical direction, resulting in a reduceddrift length and specific on-resistance. By solving2-D Poisson equation and2-DLaplace equation, the expression of the surface electric field and the RESURF criterion are derived. The influences of the trench width, trench depth, drift thickness and buriedoxide thickness of SOI LDMOS on breakdown characteristics and on-resistance areresearched. The breakdown voltage of trench SOI LDMOS depends on the minimumvalue among the following three voltages and the optimal design is achieved when thethree values are equal: the lateral voltage sustained by the oxide trench; the voltagesustained by the folded drift region; the vertical voltage sustained by both the driftregion and the buried oxide layer.. The SOI material is prepared based on Silicon DirectBonding (SDB) technology. The170~190V SOI trench LDMOS is experimentallyobtained on5μm top silicon layer over1μm buried oxide layer. The influence of thepermittivity of the trench-filling dielectric on device characteristics is also studied. Theuniveral trench design method is that the low-k dielectric is more suitable for a deep andnarrow trench while the high-k dielectric is suitable for a shallow and wide trench andthe optimal design region of the trench permittivity is obtained.4. The high voltage SOI LDMOS with a variable-k dielectric trench is proposed.The trench permittivity increases from the top to the bottom of the trench. Thelow-k material is filled on the top of the trench to strengthen the surface electric fieldand reduce the cell pitch. The high-k material is employed on the bottom of the trenchto increase the average trench permittivity and the optimal drift doping concentration.Consequently, the breakdown voltage increases and the specific on-resistance decreases.The numerical results show the specific on-resistance of SOI LDMOS with a variable-kdielectric trench is reduced by23~31%compared with that of conventional SOI trenchLDMOS.