A Cost-driven Design Of Generic Three-Dimensional Network-on-Chip

The expensive design cost has been becoming the greatest threat to continuation of the semiconductor roadmap according to ITRS’s statistics. To circumvent this issue, reuse of the existing IC designs is the trend to reduce costs of electronic products. Most traditional reuse in ICs is in the form of IP cores. With emergence of3D IC technology in which KGDs are stacked to form an integrated circuit, a bold move that the reuse is pushed to the die level has been proposed in this work.After examining the existing NoC architectures, it was found that most of the NoCs have similar architectures, which inspired the concept of GNet:a3D architecture for reusing generic network service dies (GNSDs). GNet-a3D architecture for reusing generic network service dies-is herein proposed to construct a network-on-chip (NoC) by virtue of exploiting reuse of known good dies (KGDs). In GNet, generic network service dies (GNSDs) are KGDs that integrate several networks and can be directly used to bond with other dies in3D stack. Flexible and configurable design of GNet makes it suitable to requirements in various application circumstances.Cost is often the dominant factor for decision making on architecture selection and identifying the optimal design among various design options. A comprehensive cost model, which combines the design cost model, reuse model and fabrication model, is introduced to evaluate different architectures from the design phase to the fabrication phase.By using designs whose sizes vary from16resources to256resources, the correlation between the fabrication cost and the die area was established, and an approximate optimal die area under a certain defect density has been identified. Based on the optimal die area, four GNSDs in four processes are designed. Finally, the cost comparison between the GNet implementation and the general3D IC implementation has been studied. For the GNet-based designs, the design costs would drastically drop whereas the fabrication costs would not change much within small deviations by comparison with the general3D ICs. According to statistics of ITRS, the design cost is the greatest threat to continuation of the semiconductor roadmap, and always reaches tens of millions of dollars. Since the design cost will weigh more and more in the total cost, the GNet implementation would become more superior to the traditional architectures.