Study On Key Technologies In HD STB Chip Design

High-Definition (HD) TV is a huge technological change after the digital TV. HD Set Top Box (STB) chips are important technologies to meet the demand of enjoying HD TV.The principle of Simultaneous Switching Noise (SSN) and high speed signal of the resonant circuit is analyzed in this thesis. A breakthrough is achieved in the aspects of data transmission mode of low peak power and low SSN, Double Data Rate (DDR) interface circuit modeling and high order circuit simplification, PCB chip and package co-design method and content protection of DDR bus. A success is achieved in the implementation of a HDTV STB chip and system with2-layer PCB and Quad Flat Package (QFP).The main novelties and contributions of this thesis are as follows:1. Different data transmission methods for CPU and image processing module for low peak power and low SSN are proposed. After theoretical analysis on the SSN phenomenon of DDR interface, a method of reducing SSN is proposed under constraints of QFP package. A data re-transmission mechanism based on the Data Mask (DM) signal of DDR standard is proposed according to the characteristics of CPU accessing DDR. Data Bus Invert (DBI) function of DDR4standard is implemented under DDR2/DDR3system by encoding technology according to the characteristics of image processing module accessing DDR. The results show that the loss of bandwidth is small for the data transmission with lower SSN.2. A theoretical analysis method of DDR interface circuit of2-layer PCB and QFP package is proposed, providing an effective quantitative analysis of DDR interface of HDTV STB chip with2-layer PCB and QFP package. An abstract of DDR interface circuit with2-layer PCB and QFP package as5th order circuit is proposed. The DDR output circuit is simplified according to the approximate conditions of DDR output circuit:the power supply decoupling capacitance value is more than100times the load capacitance; package inductance on the ground can be neglected compared to the package inductance on the power supply. A analysis method is discussed to simplify the5th order circuit into a linear combination of2second order circuits. The SPICE simulation results show that the analysis method is valid.3. A PCB, package and chip co-design solution is proposed, establishing a rapid evaluation system for package wire bonding design. A design scheme of DDR3compatible with DDR2is proposed according to the characteristics of2-layer PCB. A rapid evaluation system for package wire bonding design is buildup using Ruby programming language and Meta-Post scientific plotting system. The applicability of the PCB and package and chip can be checked in a few minutes.During the study for the Ph.D. and as a HD STB SOC project leader, the author participated in the high-major project of "digital TV SOC chip" and made the first successfully development of HD STB SOC with embedded domestic CPU. The SOC is commercialized in large scale. The chip is designed and tapeouted with Taiwan Semiconductor (TSMC)55nm Low Power (LP) process. DDR eye-diagram measurements are performed with different damping resistance schemes. The circuit measurement results validate the correctness of circuit analysis and design rules. A theory is raised to explain the no-monotonous waveform of DDR signal. The DDR signal data transfer rate meets1066Mbps design target with2-layer PCB and QFP package.A random delay injection based Register Transfer Level (RTL) verification method is also proposed to eliminate system functional failure caused by the meta-stable phenomenon during the chip implementation. A DDR bus protective mechanism of DES based real-time digital signal transmission with encryption and decryption is proposed, effectively preventing illegal copy from DDR bus, realizing the copyright protection of TV content. The study of this thesis helps to economize on material resources and to reduce the electronic pollutant emission during production, providing social and economical significance, and laying the groundwork for further studies on related electronic product designs.