Design Research Of SOI SiGe HBT Performance And Structure

The flexibility of the silicon-on-insulator (SOI) device architecture allows the obtaining of optimal electrical property for reduced parasitic capacitance, low leakage current, and improved immunity to substrate noise and crosstalk. Therefore, combining SiGe HBT with SOI technology, especially thin film SOI, is attractive for low power and high speed applications. A novel vertical SiGe HBT fabricated on thin film SOI substrate is proposed and integrated into the latest0.13μm millimeter-wave SiGe SOI BiCMOS technology. The device fabricated with the new technology shows decent performances, such as higher Early voltage, better trade-off between the base-collector avalanche breakdown voltage and the characteristic frequency, and better proton radiation effect. As the advantages of the device are thoroghly reported by experiments and simulations, the corresponding model should be analyzed theoretically. The purpose of the dissertation is to show how the unique features of the device can be linked to its physical origin, how they influence the electrical behaviours, and how the corresponding electrical parameters can be modelled.The work concentrates on the critical theory and technology of SOI SiGe HBT, including the properity of SiGe alloy, the physical and electrical models of SOI SiGe HBT. First, the fundamental electrical parameters such as the electric field, the potential and the depletion width are theoretically modeled, the influence of which to parasitic resistance, capacitance, characterstic frequency, and so on, are discussed. Based on the previous work, a series of electrical parameter models of the transistor effects are proposed and verified by simulation results in details, including the base-collector depletion capacitance, the Early effect and related parameters, the collector weak avalanche multiplication effect and related parameters, the collector resistance under different substrate biases, the base transit time, the base widening effect with large current and related parameters. As the structure differences between the SOI and the bulk SiGe HBT are the design of base-collector junction, the base-emitter junction can be analyzed by the conventional model, the dissertation concentrates on the base-collector junction and collector related electrical parameters. The main research work and the results are listed as follows.1. The base-collector depletion capacitance of SOI SiGe HBT is developed by considering the vertical and horizontal collector region as the series of the corresponding capacitance. The capacitances of partially and fully depleted devices are modeled respectively, with the result of dramastic reduction compared to the bulk conterparts. A smooth function is then introduced into the model for optimization based on the practical operation.2. The Early voltage model of the SOI SiGe HBT is proposed analytically. First the Early effect features of the bulk SiGe HBT with uniform or linear Ge profile in the base are analyzed, and the corresponding model of the bulk device is developed according to the original Early voltage definition with a step-by-step derivation and appropriate assumptions, then the model is generalized to the SOI SiGe HBT based on the above base-collector depletion capacitance model. It is shown that the Early voltage of the SOI device is higher than that of the bulk counterpart, and hence the current is more stable.3. The weak avalanche multiplication model of the SOI SiGe HBT is developed. The breakdown voltage BVCEO, which is depedent on the weak avalanche multiplication factor, is one of the key parameters of an HBT. As the avalanche multiplication is dominated by the impact ionization, the model is presented from the semi-emprical equation of the impact ionization factor, and applies for both the partially and fully depleted HBTs.4. The substrate bias effect on the collector resistance is modeled. As the electrical characteristics of the SOI SiGe HBT are affected by the substrate bias, the SOI SiGe HBT is equalivent to a four terminal device and it is inevitable to research the substrate bias effect. The influence of the substrate bias on the collector resistance is analyzed in detail, resulting in a lower resistance and hence a larger characteristic frequency under positive bias compared to that of zero substrate bias.5. The base transit time and the base width widening effect models are proposed analytically. The change trends of the corresponding parameters are obtained.