Study Of High-Resolution ∑△ Analog To Digital Converter

The oversampling∑△(Sigma Delta) Analog to Digital converters(ADCs) arecurrently one of the mostly prevailing architectures for the high-resolution ADCs. It iswidely applied to audio, digital TV and wireless communication. It is a hot anddifficult topic to design the stability∑△ADC with high performance and high-order.This dissertation focuses on the research of the high-resolution and high-order∑△ADCs on a background of National Defence Preliminary Research Project and BeijingMicroelectronics Technology Institute Research Project. The theory of high-resolutionand high-order∑△ADC is systematically studied. The main research works andcreative contributions of this dissertation are as follows:1. As a chief member, the author accomplished the design and test work of anaudio 16-bit single-stage 5-order 1-bit CRFF∑△ADC with overload stabilityand dynamic DC dither technique. The chip was implemented in 0.5-μm 5-VCMOS technology. The die area occupies only 4.1 *2.4mm~2. The powerconsumption is only as low as 90mW. The chip has been tapped outsuccessfully.2. An optimal design method for single-stage high-order 1-bit∑△modulator isproposed and applied to reasonably select and design a single-stage 5-order1-bit CRFF∑△modulator basing on the power consumption, satisfying thedesign specifications.3. A digital-switch stability method is proposed, based on reducing the order ofthe modulator and resetting integrator. Overload recovery speed is faster thanthe methods which were proposed by Pneumatikakis and T. H. Kuo. Thisstability method can be applied to single-stage any-order 1-bit CRFF∑△modulator.4. A dynamic DC dither technique is proposed to eliminate the tones. Thetechnique can reduce about 2/3 area of digital circuits compared to the dynamicAC dither technique, proposed by Norsworthy, at the cost of a little loss ofSNR.5. Several math models of system level simulation are designed to take intoaccount of the non-ideal factors, such as circuit noises and switched-capacitorcircuits. The presented models can be used to determine the requiredspecifications in circuit level simulation. A 16-bit single-stage 5-order 1-bitCRFF∑△modulator has been designed by using the required specifications.The models of system level simulation are effective on circuit design accordingto the results of circuit level simulation. The FOM-w value for evaluating the∑△modulator performance is 8.3(the ideal value of FOM-w＜10). It showsthe modulator has good performance.6. A poly-phase transformable stage non-recursive comb filter architecture isproposed. The proposed filter has saved 45% area and 35% power consumptioncompared to the conventional one in designing the same clock frequency of thecircuits. The actual chip test scheme and test evaluation fixture are designed. Testenvironment is established. The primary test results of the chip are successfullyoptained.