Design And Verification Of Vector Processor For Audio Signal Processing

Real-time audio signal processing in embedded systems requires the processing system to have sufficient parallel processing capabilities and also needs to retain a certain degree of versatility to cover more application scenarios,given the varying accuracy needed in different application scenarios.RISC-V vector instruction set,as the latest vector architecture instruction set in recent years,boasts a more independent instruction function,more concise processing of any vector length,and the instruction coding closely matching the RISC-V scalar instruction set compared with the architectural definition of other vector instruction sets.However,there is not yet a general implementation scheme for extending the support for RISC-V vector instructions,especially vector memory access instructions,in scalar processors.In this thesis,the problems to be solved to implement vector instruction extensions outside the scalar unit are analyzed from the perspective of the core microarchitecture of the scalar processor,on which basis a general method is proposed for the implementation of RISC-V vector processing system hardware.The vector instruction function of the open-source scalar processor is extended and based on the data types matched by audio signal processing and the arithmetic operations contained in the processing algorithm,a continuous memory access unit that adapts to the vector data size and a minimum arithmetic unit that meets the application requirements of audio signal processing are designed and implemented.Audio signal processing algorithms implement the same computational steps for multiple sample points through a large number of loops.But there is no matching vector instruction in the vector instruction set to meet the special calculation requirements of multiple sampling points at the same time.Therefore,in executing sub-loops at multiple sampling points,the vector processor can only execute the relevant audio processing steps through multiple scalar instructions.This,in addition to the slow speed,also let the vector calculation paths inside the vector processor lie idle.In this thesis,the implementation scheme of the custom instructions is proposed based on the principle of compiling the RISC-V vector instruction set.The corresponding custom instructions for the audio preprocessing vector algorithms are also designed to verify the feasibility of the method.The method does not require modification of the compiler and uses custom instructions to allow related audio processing algorithms to be executed in parallel inside the vector processor,it could be taken as the audio processing algorithms executed with parallel effects equivalent to vector instructions.To sum up,the embedded audio signal processing system architecture is tailored according to workloads and implementations of audio signal processing,a domainspecific processor that is highly compatible with the algorithms and data types in audio signal processing is designed,and the experimental results show that the vector processor achieves a maximum optimization of about 11.72 times the number of instructions and about 6.75 times the number of clock cycles with 2.9 times the area of the scalar processor.The pre-emphasis,FFT,and power spectrum operations are performed with matching custom instructions and hardware scheduling logic,achieving processing speedups of approximately 2.94 times,5.20 times,and 3.70 times,respectively.The balance between performance and power consumption is stricken with a highly customized system design.