Research On VLSI Implementation Of The Variable Universe Adaptive Fuzzy Logic Controller

Fuzzy logic controller (FLC) had been effectively used in many areas. However, the conventional FLCs with fixed control rules will not perform well due to the lack of self-study or adaptive ability. Therefore, it is necessary to study adaptive fuzzy logic controllers (AFLCs) and their circuit implementation. At present, most of the AFLC chips are difficult for analog circuit implementation because they are based on adapting the antecedents and/or consequences of fuzzy rules on-line, which requires large calculation and storage resources. So far there has not been a complete fabricated analog/mixed-signal chip of this kind of AFLCs. Variable universe adaptive fuzzy logic controller (VFLC) is a stable controller which improves the control effect by changing the input and output universes. It has only a few on-line adapting parameters of input and output universe contraction factors, thus is suitable for hardware implementation, while its circuit implementation has not been reported before. Therefore, its VLSI implementations are proposed and studied in this dissertation. The main work and highlights include:The VLFC algorithm is improved to make it more suitable for VLSI implementation. A novel peaky-triangle membership function is proposed to fulfill the function of the complex input universe variation directly, which reduces its complexity greatly. The output universe contract factor of the VFLC is improved by introducing an absolute value to its original method, which is the integral of the input variables. The digital architecture of the VFLC is proposed and developed using Verilog-HDL hardware description language. The closed-loop of a nonlinear object controlled by this ditital VFLC system is simulated under a co-simulation environment composed of ActiveHDL and Matlab/Simulink, which verifies the functionality of the digital VFLC system.Functional blocks and a whole analog system of a conventional 0-order T-S fuzzy logic controller is proposed and implemented, including new compact-structured membership function circuits, current-mode minimization circuits, multipliers and a center of gravity defuzzification circuit.A fully on-chip adaptive 2-input 1-output analog VFLC chip is proposed and implemented here for the first time, using a 0.6μm CMOS standard technology provided by CSMC. An "all-purpose"membership function circuit is proposed to generate a special peaky-triangle for the VFLC input variable universe, as well as to generate conventional Z-type, Gaussian and S-type membership function when applied with different reference voltages. Thus with the proper configuration, this VFLC can work in either adaptive or non-adaptive mode, which increases its application area. The output universe contraction factor is constructed by an integrator and an absolute value circuit. A PCB board is made to measure the VFLC chip. The measurement results show that it completes the VFLC functions, with an inference speed of 200K FLIPS, power consumption of 10mW, core chip area of 1.1mm2, interfaces of voltage/voltage, and off-chip requirement of only resistances and capacitors. Compared with other fabricated adaptive FLC chips, this VFLC chip has advantages in chip area, interface style and off-chip components configuration.