Study On Key Technologies Of IP Based SOC Design

With the rapid development of SOC (System on a Chip), IP cores must meet the increasing need for standardization and robustness. However, the adaptability of the interface timing and configurability of parameters of IP core have limited the development of SOC. In order to solve the problems above, this dissertation investigates such key issues as interface timing bottleneck and IP function customization in the current design of SOC, and proposes Timing Padded Cell Resynchronous Module (TPCR), including the padded interface and re-synchronization of the interface, and configurability of parameters of IP core. Using above techniques, we have completed the design of USB 2.0 core and 8-bit embedded CPU core.Firstly, the dissertation studies the padded interface of the reusable IP cores and proposed the TPCR IP core model. The interface timing of traditional IP cores lacks flexibility, resulting in convergence time of the timing very long, even non-convergent. This problem can be solved by adopting parameter configuring and TPCR model. The TPCR IP core is made up of the padded delay cell and re-synchronization cell. The padded delay cell specifies and restricts the interface timing of the IP core, making it possible for the SOC designers to estimate the margin of the interface timing at every design stage and making the IP core integrated in SOC seamlessly without the glued logic. The re-synchronization cell bridges different clock domains and asynchronous signals, ensuring that IP core carries out the transfer of the asynchronous signals. In addition, digital controllable ports of the padded delay cell are parametric, so the parameter can be configured at different design stages to change delay and offer flexible timing of IP core interface. The method of IP core design based on TPCR model has been applied in the design of SOC, greatly accelerating the timing convergence.Secondly, the dissertation presents the design of a USB 2.0 IP core whose parameters can be configured, including PHY IP and LINK IP, and explores the method of designing a parametric LINK IP. Parameters are used in defining endpoint, type, transport, input/output memory and FIFO depth of the LINK IP core. The re-synchronization technology is adopted in the design of AP data interface for separating the USB clock from AP clock, so the IP core can be connected smoothly with the AP module, and the range of choices for the components in the AP side is widened. AP interface buses and UTMI data buses are also parametric to match IP cores with different interfaces through modifying the parameters, thus establishing the communication among IP cores. The minimum capability of 1 general endpoint and 1 transport mode per endpoint and the maximum capability of 15 general endpoint and 4 transport modes per endpoint can be achieved through changing the parameters. Furthermore, padded delays are used in both PHY IP and LINK IP core to adjust the interface delay and diminish the problem of un-matching interface delays. In order to validate the techniques of TPCR and parameter configuring, the layouts of PHY and LINK IP core were designed and fabricated with the use of 0.25μm CMOS technology in SMIC. The results show the range of interface timing of the USB IP core is wide and can be fit to more external IP interface timings; and with parameter configuration, the scale of the IP core is flexible so as to meet different design needs.Since embedded processor IP core has been in wide use, in this thesis, an 8-bit parametric embedded MCU IP core, XDMARC, is designed, which includes ALU, general register files and instruction decoder, compatible with the AVR instruction set. Modifying the parameters yields a scale of about 8000 gates in the minimum mode when the IP core support AVR instruction set and GPIO, and over 20000 gates in the maximum mode when the IP core support AVR multiple instructions and more peripheral devices. Simulation results show the performance of the minimum mode can reach 200MIPS under the condition of SMIC 0.25μm CMOS technology. Parametric design methods are also utilized in the design of peripheral components. The instruction set can be selected through parameter configuration to reduce the function and peripheral components. And the interface of the IP core is designed with the introduction TPCR technique, whose delay parameters can be modified in the stages of system design, simulation verification or layout design, based on the requirements of integration conditions. So, XDMARC enjoys a high adaptability to more bus structures and offers more freedom in place and routing. And the design iteration coming from the timing convergence requirement has been decreased.Finally, the USB, XDMARC and other IP cores (UART and SRAM etc.) in this research are integrated into an SOC. Results show the use of TPCR speeds up the timing convergence efficiently and improves timing adaptability of IP core interface. With parameter configuration, the IP core is found to have better adaptability so as to meet different design requirements, increase the reusability of IP core and bring down the cost of SOC design and fabrication.