Research On IF Digital Transceivers And System Implementation

At present, with the developments of techniques, more and more transceivers are fitted to be implemented with digital techniques. Because digital techniques are superior to their analog counterparts in aspects of higher accuracy, higher agility, smaller volume , lower power dissipation as well as better anti-jamming capacity. The ideal SDR requires ADC and DAC as close to the RF front end as possible, and realize as much as possible radio functions with software. Nowadays, SDR transceivers are suited to be realized at intermediate frequency due to the restrictions of chip manufacturing techniques. Researches are focus on all digital modulation demodulation structures and algorithms on the one hand and, and on the another hand on developing prototype with high speed A/D, D/A converters and high performance, large scale programmable chips. These efforts are of great importance to realize ideal SDR in the sense of theories and practices.This thesis discusses some topics of designing IF digital transceivers. The first topic is about all digital PCM/FM telemetry receiver whose data rate is 2Mbps. Three items are included: 1) A new effective digital FM demodulation algorithm has been presented; 2) Carrier and PCM code synchronization techniques have been explored and a new carrier deviation suppression algorithm has been proposed; 3) A prototype of PCM/FM digital receiver which is designed and implemented with high speed ADC, dedicated DDC and FPGA has been tested in the lab. Because typical DDC method is hard to receive wideband signals, the second topic of the thesis is about effective wideband DDC implementation structures. Four structures have been studied, which can overcome difficulties of typical DDC method effectively. Design of all digital high data rate transmission transceivers is the key techniques of the TDRSS systems. The third topic of the thesis is concerned with the problem designing 800Mbps 8PSK receiver, two main items are included: 1) Implementation scheme and 8PSK demodulation algorithms have been proposed, which are performed in the frequency domain in parallel and verified by computer simulations; 2) A prototype of 8PSK receiver which is designed and implemented with super high speed A/D converter and high performance FPGA has been tested in the lab. The fourth topic of the thesis is about digital IF modulation and frequency synthesis techniques, three items are involved: 1) A four channel multimode digital IF modulator has been implemented based on the ICS-564A DAC card; 2) Implementation scheme of 800Mbps 8PSK wideband digital modulator has been put forward. A prototype which is designed with high performance FPGA and super high speed D/A converter has been tested in the lab; 3) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid synthesis techniques, which can cover the S,L and C bands at one time.The main creative points in this thesis are as follows:1) In the research of the PCM/FM IF digital receiver, a high effective FM demodulation algorithm has been presented, which performs phase discrimination with CORDIC algorithm and then first order differential frequency discrimination to the phase discriminated results and is suited to be realized with FPGA in the form of multi-stage streamlined structure.2) Carrier and timing synchronization techniques of the PCM/FM IF digital receiver have been studied. A new carrier deviation suppression algorithm has been proposed that can perform envelope detection with a slip window and then subtract detected results from the received signals, which consumes little amount of calculations and is adaptive to carrier variation.3) A PCM/FM IF digital receiver has been implemented with IF sampling ADC, dedicated DDC and FPGA, which has better performances and is verified by experimental results.4) Four effective wideband DDC implementation structure have been researched: mixer postpositional structure, the minimum common multiples structure, once frequency transfer structure and double frequency transfer structure, which can decrease multiplication speed of filtering and mixing in effect.5) Implementation scheme and demodulation algorithms of 800Mbps 8PSK receiver have been presented which are performed in the frequency domain in parallel and verified by computer simulations.6) An 800Mbps 8PSK receiver has been implemented with super high speed A/D converter and high performance FPGA, which can demodulate 8PSK signals correctly.7) Design scheme of 800Mbps 8PSK IF modulator has been presented. A prototype has been implemented with high performance FPGA and super high speed D/A converter, which has better EVM performances verified by the experimental results.8) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid frequency synthesize technique which has better performances and can cover the L, S, C bands at one time.