Novel Source-Drain Design For Extremely Scaled Mosfets

With the countinous shrinking of MOSFET, both the gate dielectric thickness and the source/drain junction depth have been continuously reduced accordingly so far in order to effectively suppress short-channel effects. However, as the feature sizes of MOSFET scale down into nanometer regime, ultra shallow source/drain junction has caused the increasing process difficulty and severe parastical issues, so source/drain technology is rendering the further scaling of device dimensions difficult. Therefore, innovatory source/drain technologies have been paid much attention recently. In this paper, two novel source/drain technologies are proposed and studied based on the results of simulations and experiments.The first source/drain technology proposed is"Novel Schottky S/D MOSFET". Schottky S/D is a promising structure to solve the source/drain issue in the future. However, conventional Schottky S/D MOSFET shows worse off-state performance. Therefore, two improved structures are proposed to obtain better performance in this paper. The first one is"Asymmetric Schottky S/D MOSFET (ASSD MOSFET)", which characterizes in that source/drain Schottky barriers are asymmetric, wherein the source has a higher Schottky barrier and the drain has a lower Schottky barrier. The second one is"Dual Schottky S/D MOSFET (DSSD MOSFET)", which characterizes in that the source/drain is a dual layer structure with a lower top layer Schottky barrier and a lower bottom layer Schottky barrier. Simulation results show that the improved off-state performance can be obtained using these two structures. In addition, the self-aligned processes to fabricate these two structures are also proposed. The second source/drain technology proposed is"TSB MSOFET", which characterizes in that the source and drain regions except for the lateral sides connecting to the channel are insulated from the substrate,while the channel region is in the substrate and doped in a step-function (extremely retrograde). Simulatation results show the new design provides nano-scale devices with better or similar short channel effect immunity and subthreshold characteristics than or to conventional bulk silicon and UTB schemes. A process fabrication method is designed and demonstrated. Experimental results show the fabricated TSB MOSFET matched with the results of theory analases and simulatation exactly. Meanwhile, a self-aligned process for fabricating the device with the proposed design is also proposed.