Researches On Architecture Of Highly Reliable On-board Computing System Based On Reconfigurable Computing

The development of aerospace technology is very important to different nations and human beings in whole. It is a sign of the comprehensive national strength and the research and development capability in advanced science and technology. The aerospace technology has great impacts on military technology, national defence, economy, as well as many other related fields. Recently, many countries have launched various large-scale aerospace exploring projects, such as manned orbit flight, manned moon landing, trip to Mars and so on. OBCS (on-board computing system) is the application of computing technology in outer space environment, and it fulfils the tasks like aerocraft control, communication and on-board data processing. Due to the poor working conditions in outer space, it is a great challenge for OBCS to achieve good performances in speed, reliability and cost simultaneously. The high manufacture cost and limited budget has made it a demanding job to implement a fast and reliable OBCS which is vital to any space exploration mission.Space Solar Telescope (SST) is a scientific space research project, which will send a solar telescope into outer space to overcome the negative effects of Earth atmosphere. With SST project as the background, the paper aims to solve the key challenges in designing a reliable OBCS with high performance. Such challenges include system architecture, fault diagnostic and recovery methods. By analyzing the development and the characteristics of reconfigurable computing technology, the paper finds out that the dynamic reconfiguration technology can meet the requirements which OBCS imposes on the performance, reliability and cost. A modular architecture based on LEON 2 IP (Intelligence Property) core is proposed, which supports dynamic reconfiguration, and is able to boost system performance and flexibility. In this architecture, a dynamic reconfigurable module is used to process the huge data in order to exploit the advantage of parallelism nature of reconfigurable hardware. The dynamic reconfigurable module communicates with LEON 2 processor IP core via a generic co-processor interface, providing better flexibility than special interfaces. To enhance system reliability, an improved TMR (Triple Module Redundancy) scheme and a methodology to detect and remove faults are also provided. The fault detection and recovery methodology is based on the configuration bitstream (configuration data). To simplify the fault detection and recovery implementation, JBits is employed to deal with the configuration data and hardware reconfiguration operation. Markov process theory is used to model and evaluate the reliability of the system which can be repaired through hardware reconfiguration. The analysis results show that our approach of fault detection and recovery can improve the reliability of system. To facilitate the design and implementation of modular dynamic reconfigurable OBCS, the basic system design process and some implementation techniques are explored. Their feasibility and effectiveness are demonstrated by building a prototype system. By running an FFT benchmark test task, the performance of the reconfigurable prototype system is evaluated and compared with some systems of different architectures such as 80386 and ADSP 21020. The testing results indicate that: the performance of dynamic reconfigurable system is much higher than other competitors in case of processing large amount of data continuously. Simulation results on routes fault recovery using JBits/JRoute are also given, which proves that, JRoute can find a new route to replace the faulty one automatically after a route fault has newly occurred.