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Design Of The Mixers For WLAN 802.11a/b/g/n Transceivers

Posted on:2012-01-25Degree:MasterType:Thesis
Country:ChinaCandidate:Y D JiangFull Text:PDF
GTID:2178330335465913Subject:Microelectronics and Solid State Electronics
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With the growing popularity of the handheld mobile communication devices, such as tablet PCs, smart phones, e-books, and the rapid development of Internet applications and e-commerce, users need to connect to a wireless network at any time. In the field of wireless LAN, there are emerging new technologies and standards. On one hand, only multi-mode multi-band terminals can be used to realize flexible and convenient communication; on the other hand, the worse case of the wireless channel, makes more demanding performance requirements of the RF circuits in transceivers.In this thesis, a chip of mixers which applied in wireless LAN transceivers is designed and fabricated in 0.13μm CMOS process. The up/down conversion mixers cover 5-6GHz and 2.4-2.5GHz bands, and support IEEE 802.11a/b/g/n standards. The main achievements are shown as follows:(1) Based on thorough study of the 802.11a/b/g/n high-speed wireless LAN standards, the disadvantages and advantages of typical transceiver configuration are analysed, and detail design specifications of the mixers are given.(2) A quadrature down conversion active mixer structure (patent NO. 201010190546.X) is presented, which supports 802.11a and 802.11b/g/n standards respectively. The topology is based on the folded Gilbert mixer. Current-reuse techique is added in the complementary transconductance stage to enhance the conversion gain. Current bleeding technique in the switch stage decreases the noise figure. An on-chip input impedance matching network is also included. It realizes the trade-off among linearity, conversion gain and noise figure successfully.(3) A stacked quadrature up conversion active Gilbert mixer, which supports 802.11a and 802.11b/g/n standards is studied. The influence of the transconductance transistor sizes and bias currents on the mixer performance are analysed. An on-chip output impedance matching network is included to be cascaded with PA and RF measurement equipments.(4) The chip is achieved on 0.13μm RF CMOS process. The measurement results are shown as follows:for the 2.4-2.5GHz down-mixer, conversion gain is 4dB, NF is about 11.2dB, and IIP3 is about 5dBm; for 2.4-2.5GHz up-mixer, conversion gain is above 3dB, OP1dB is about 4dBm, and NF is 13dB; for the 5-6GHz down-mixer, conversion gain is more than 5.5dB, IIP3 is as high as 11dBm, and NF is about 12.8dB; for the 5-6GHz up-mixer, conversion gain is as high as 3dB, OP1dB is about 2.5dBm, and NF is about 17dB. The results meet the specifications requied by the transceiver absolutely.This thesis'work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number: 2009ZX01034-002-002-001-02).
Keywords/Search Tags:high-speed wireless LAN, mixer, conversion gain, linearity, noise figure
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