.32 5 Pipeline Embedded Processor Design

Embedded processors are increasingly used in digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car information systems. With the dramatic increase in consumer electronic market, the embedded processor market is increasing at a rapid rate. Some of the key goals for traditional embedded processors design are low cost, small area, and low power. With the need for high performance in embedded applications increasing, the demand for high performance 32-bit embedded processor from market rise sharply. So it is important to research design 32-bit embedded processor.In this paper we present the Beta Instruction Set Architecture, including machine model, instruction encoding, instruction specifications, extensions for exception handling and software conventions. We designed Beta5, a 32-bit embedded processor based on Beta Instruction Set Architecture. Beta5 is a 32-bit harvard-architecture RISC CPU, with 5-stage pipelining, full bypass, and cache system, including 16 KB instruction cache and data cache. We also integrated a branch predictor in Beta5 for increasing performance. This paper describes the design and implementation of Beta5, including structure design, pipelining design, bypass design, cache system design, and branch predictor design. In this paper we also introduce the design flow of Beta5, including simulation with behavioral models, simulation with RTL models, synthesize our design in FPGA, and debugging hardware using ChipScope Pro.