Study On The Image Pre-processing Method And System Software For Staring IR Imaging Information Processing System

Staring infrared imaging system based on the Infrared Focal Plane Array (IRFPA) technology has become a main trend of development in the field of infrared imaging system. Unfortunately, it is well known that the performance of the staring IR imaging system is mostly affected by IRFPA's spatial photoresponse nonuniformity and non-effective pixels (or dead/noisy pixels). To remedy this problem, nonuniformity correction (NUC) and non-effective pixels detection/compensation for IRFPA should be applied, and those techniques are important issues in staring IR imaging information processing system. Another important issue is the operating system software of the IR imaging parallel processing system, which provided parallel processing environment for image processing algorithms. This dissertation is arranged around the problems cited above, including IRFPA NUC, IRFPA non-effective pixels detection, IRFPA NUC and non-effective pixels compensation implemented by hardware, and the embedded operating system software of the IR imaging parallel processing system. The main contributions are given below. For the nonuniformity in IRFPA, calibration-based and scene-based (adaptive) NUC techniques are both studied in this dissertation. Based on the principle of the calibration-based NUC technique and the nonlinearity of the photoresponse characteristic, optimal piecewise linear NUC method and optimal polynomial NUC method are proposed which are suitable for real-time implement. Comparing to the similar widely used NUC schemes, those proposed approaches can achieve better NUC performance. In the aspects of adaptive NUC technique, an in-depth analysis is made of the cause of object degeneration and ghosting artifact in neural networks based NUC (NN-NUC) scheme, and the disadvantage of NN-NUC denoising the low frequency dominated nonuniformity noise is also studied. The roots of those problems are pointed out, and then an edge-directed NN-NUC scheme (ED-NN-NUC) and a NUC method integrating one-point correction with ED-NN-NUC are proposed. Comparison experiments with simulated data and real IRFPA infrared data shows that those proposed schemes are rational and effective. To achieve the non-effective pixels detection, the problem is equally regarded as the effective pixels detection, and then a new approach of IRFPA non-effective pixels detection based on pixel's characteristics histogram decomposition is proposed. Comparing to the mostly used method, the proposed approach fully takes into account the response characteristic of the effective pixels, therefore better detection performance can be got ultimately. Furthermore, a two-stage search fast algorithm to realize the histogram decomposition is also presented. Since the fast algorithm is based on multi-resolve principle, it is more efficient and more effective than the old one. To realize IRFPA real-time nonuniformity correction and non-effective pixels compensation, an IR image pre-processing hardware module is designed and implemented using the field programmable gate array (FPGA) technology. Comparing to the existing designs, the presented method can correctly compensates the spatially continued non-effective pixels, moreover, it can fully economizes hardware resource (including logic unit and memory resource) and ensures the appointed correction precision at the same time. Therefore the proposed design is very suitable for the miniaturization of IR image processing system. To provide a convenient and reliable parallel processing platform for image processing algorithms, a parallel image processing-oriented real-time embedded operating system (PIPORTEOS) was designed and implemented for the IR imaging parallel processing system, which is based on multicomputers architectures and consists of multi-DSPs. PIPORTEOS is based on microkernel architecture, and implements a distributed message mechanism to support parallel processing. PIPORTEOS has well real-time, portable and reliable performance, and at present it can run on the fixed-point digital signal processor (DSP) TMS32OC64 chip and the float-point DSP TMS32OC67 chip of TI Corp.