Design And Implementation Of Multi-Mode WLAN Baseband SoC SyStem

The Technology of Software Define Radio (SDR) is able to change dynamically the way of communication of wireless terminals only through downloading different kinds of software. As another revolution in wireless communication field, this technology will change significantly the appearance of it. An important aspect of SDR is the multi-mode baseband processor design and realization, which have became a research hot point both in Industry and Academy.A multi-mode baseband processor based on IEEE 802.11a/b is designed and realized using the SDR technology in this paper. First of all, a wireless channel fading model suitable for WLAN application is analyzed and designed, with which, the baseband algorithm and performance of baseband processor is verified and simulated. Based on the behavioral level simulation, the most important baseband algorithms, such as timing sync, freq sync, phase compensation and channel estimation, are analyzed. The characteristic of algorithm realization, calculation amount and optimized parameter is decided during the simulation.Second, according to the requirement of 802.11a/b baseband protocol and the result of algorithm analysis, an effective SW/HW partition rule is proposed, under which, an implementation architecture of ASIP+Accelerator+SoC Bus is designed creatively. This design is of highly flexibility, parallelism, extensibility and keeping the small chip area, very low power at the same time.Third, as we all know, access to memory system is one of key factor that affect the whole system performance. In this paper, a highly effective memory system is designed. It has the characteristics of wide data throughput bandwidth, automatic address generation and DMA. These characteristics enable the minimized memory access times, and therefore, lower down the system power.Fourth, algorithm flow of firmware design is arranged in time according to the requirement of 802.11 a/b baseband protocol and the result of algorithm analysis.At last, this designed SoC chip is taped out by 0.18um CMOS process. A test environment especially for this chip is build. After loaded the firmware, this chip is working well by transmitting and receving the testbench. The test result show, this system architecture proposed in this paper is one of effective way to implement the wireless multi-mode baseband processor.