Research On Boolean Process-Based EDA Methods Considering Interconnect Effect

The technology treatment with IC in VDSM, for example logic level simulation, ATPG, routing and placement, must consider the interconnect effect. Otherwise the characteristic of circuits can not be reflected more factually, some extensions are done on the waveform computing in Boolean Process in this dissertation, by which some new algoritms considering interconnect effect are discussed in above four technologies.Interconnect effect, especially crosstalk disturbs the logic and time sequence badly, the traditional logic level simulation can not reflect the factual state of circuit. So interconnect effect must be considered in simulation technology. The layout simulation must be done for considering the factors exactly. Coupling capacitance and dynamic switches of signals are two important crosstalk factor. Dynamic switches of signals decide the generation of crosstalk. So the waveforms relation generated by logic level simulation has important effect on the estimation and optimization of crosstalk. The power of circuit can be estimated more exactly by the sum of switches of circuit generated by the simulation considering interconnect effect.A Boolean Process-based logic level simulation method is presented in this dissertation. Some critical problems, for example hazards finding, feedback cycle treatment, false paths finding and inertial delay conflict, are described, analysed and solved. The hazards finding theory is a formal method to find hazards in circuit by computing waveforms. Time piece method and waveform increase algorithm solve the defect of Boolean Process in feedback cycle treatment. False path finding algorithm can the redundant part in netlist. inertial conflict elimination can describe waveforms more exactly. Utilizing above concepts and results, a parallel algorithm for logic level simulation is presented. It need not partition the data, but forms the active components queue to realize parallel computing in simulation. The algorithm improves acceleration ratio by scheduling priority.For simulating the logic waveforms in interconnect effect, the ' interconnect component' is defined, including its original waveform, crosstalk waveform and interconnect transport gate. A Boolean Process-based computing method for crosstalk waveforms on nets is presented after obtaining layout information. The Logic-Crosstalk Graph is defined. It integrates the basic algorithm of logic level simulation and corsstalk computing, by which the waveforms simulation considering interconnect effect can be performed. The crosstalk delay computing of interconnect are described in VHDL.Aiming at the sensitization concept in Boolean Process, the computing rules of sensitization waveforms sets with time windows are defined, the method generating test waveforms in crosstalk is presented.For minimizing crosstalk in detailed routing, the distance between waveforms in Boolean Process is defined newly. Integrating coupling capacitance, the crosstalk between nets is defined. Based on above work, the object function for minimizing crosstalk in two-layer detailed routing is presented. It can reflect the crosstalk between nets more exactly and afford more space for adjusting routing. Routing generating tree and improved GA are presented, by which the channel routing method with minimizing crosstalk is designed. It can reduce the cost of computing. Variable parameter method is presented to design the routing algorithm with optimizing crosstalk, and the routing resource is utilized fully. Above methods have potential parallelism because of computing of all nets is performed simultaneity.The waveform computing considering interconnect effect can be utilized to estimate the power of circuit more exactly. So a macrocell placement algorithm that both minimizes length of wires and distributes power equably is presented. It considers the position of cell' pins, makes the minimizing of length of wires more flexible. The confirming of power centre makes the picking up of power more convenient. Algorithm decomposes big scale placement optimization by grouping and reduces the sum of wires by integrating.