Research Of Local Homogenous Yet Global Heterogeneous DSP Processor Design

Owing to the booming of signal processing and the subdivision of application domains, the current DSPs (digital signal processor) have to be faced with severe challenge of the diversification and specification of algorithms. To meet such demands, how to rapidly design the suitable DSP becomes the key problem of digital signal processing system.The author attended the 16-bit DSP-MD16 and its development tools design projects. With these basements, the paper demonstrates the main aspects of DSP architecture design, key realization, MAC design and HW/SW co-simulation/co-validation, and attempts to construct an integrated philosophy of DSP design, simulation and validation to meet the not heavy digital signal processing requirements, thereby shorten the time-to-market.The main contents and innovative points in this paper include:> Puts up the idea of constructing the local-homogenous yet global-heterogeneous DSP philosophy. Arithmetic series operating codes strategy is applied to banlance the probabilities and functionalities of instructions. Through elablishing the relation between operands codes and register structure, the register structure design is translated to the optimaztion of operands codes in finite field and RISC-like local-homogenous register set is adopted finally. Two-dimensional extended LAOD/STORE mechanism is utilized to enhance the memory access capabilities. For the circular addressing, a virtual boundary circular addressing method is presented to solve the consecutive placement of arries in memory. To improve the code density, the scheme of parallel implementing register-oriented computation and extended LAOD/STORE is utilized to improve the DSP executing efficiency. MD16 embodied realization reqirements and pipeline-partitioning principles are indicated according to script of the local-homogenous yet global-heterogeneous DSP architecuture. Through comparing different partition strategies and reasonably arranging the instruction actions, four-stage RISC-like pipeline with extended EX stage strategy is adopted to decrease the control/data dependency and satisfy the frequency and timing demands. Also the RISC-like instructions, complex DSP instructions and multi-operation instructions are fused together with the sole pipeline. Presents the idea of constructing the general MAC platform based on the minimal merging of multi-mode multiplication algorithms to well satisfy all kinds of requirements and improve the efficiency of DSP. For the partial products generation, the novel method of Booth encoding combined with partial products generating is put up, which can directly map the multiplicand and multiplicator to partition products without generating the BOOTH encoding results. For the optimization of Wallace tree adding, the series formulas of full-adder and 4-2 Compressor realization are introduced to guidance the selection. For the non-bias round, forwarding round disposal in Wallace tree method is brought forward to avoid the final multi-bit adder. Also, the idea of delay-oriented partition of the MAC frame is put up to achieve the perfect match with multi-pipeline DSP architecture. MD16 simulation/verification platform is studied in this paper. Through the separate/cooperative simulation and verification of C-depiction oriented PC sub-platform, HDL-depiction oriented Virtual Machine sub-platform and FPGA hardware sub-platform, MD16 processor can be sufficiently validated.MD16 chip has been successful fabricated and validated. Under the condition of SMIC 0.18μm CMOS technology, the chip can run from 0 to 162MHz with the power consumption of 1.1 mW/MHz.