Research And Design Of Cmos Bluetooth Radio Transmitter

Bluetooth is a low cost, low power, short distance wireless communication technology. In recent years, the expansion of Bluetooth products and wireless technology applications, and the continuous development of CMOS process, make the research and realization of low cost CMOS integrated wireless transceiver important not only in economics, but in academics.This paper focuses on research and design of CMOS integrated Bluetooth transmitter. The architectures of wireless transmitter are divided into two groups: Mixer based architecture of Class I and Loop architecture of Class II. Since the former accords better with the trends of wireless developing, a low-IF transmitter architecture is used for Bluetooth in this paper. The circuits of GFSK, Up-conversion Mixer and Power Amplifier in the transmitter are designed respectively.GFSK digital modulation is realized using Look-up Table and DDFS, this circuit and 7bit current-steering DAC & Gm-C low pass filter accomplish the whole GFSK modulation function. The size of ROM in DDFS circuit is compressed to 1/12 by triangle equation arithmetic. In DAC, the precision of current source is improved by using segment architecture and optimized array, the resolution achieves 1 LSB and DNL is in the range of +0.5LSB; In Gm-C filter, linearity of Gm cell is enhanced through a pair of source-degenerated differential CMOS transistors, whose rds can vary with the amplitude of input signals, the variation of Gm is below 2% when the amplitude of input differential signals is in 900mV.With the RF switch MOS driven by the small signals, the double-balanced Gilbert up-conversion Mixer outputs low harmonics, the linearity of low frequency MOS is also improved by a V-I conversion cell; Many efforts are focused on the design of Class AB Power Amplifier, which has a two-stage structure. The input stage amplifies signal amplitude, and band-passes the signal. The output stage design integrates the parasitics of package, which ensures both maximum power output and the purity of frequency spectrum. On-chip inductor and coupling capacitor are also designed; Two solutions to alleviate the influence of package parasitics on circuit performance are brought forward, for the signal case, odd-mode excitation theory of differential line is adopted to reduce the parasitic inductance of package by 50% or more, for the case of power supply (ground), a series resistor is introduced to degrade the Q of parasitic inductor of package and the possibility of oscillation is reduced greatly. The simulation results show that the maximum output power of the transmitter is up to 14dBm, and PAE of the Power Amplifier reaches 45.7%.After the completion of circuit and layout design, the transmitter is fabricated twice in 0.35um CMOS process. The measurement results for the firstly fabricatedchip show that the total static current under the power supply of 3.3V is 19mA, close to its foreign counterparts, the performances of both low-frequency DAC and low-pass filter meet their design specifications, and the RF circuit realizes RF signal power controlling and transmission. The test of the secondly fabricated chip is underway, and from the rough measurement results, the performance of the transmitter can be expected to be better.