Vlsi P / G Network Authentication And Macrocell Wiring

Hierarchy methodology is an effective way to solve complicated problems. It is also the essential systematization means. Layout synthesis and design verification are extreme complex problem. On the one hand, the size of the problem is enormous. For example, there are more than several million transistors in a single chip. On the other hand, along with the technique developing, the typical wiring width has arrived the deep sub micron stage; the frequency has been GHz level. Placement and Routing must satisfy multi-goal and multi-restriction. Design verification must consider much more circuit parameters and complicate influence. The paper can be divided into two partitions: In the first part the P/G network verification problem in the VLSI chip scope is probed. An algorithm is proposed which partition the global network into several sub networks. Then it performs sub network compressing equivalent transform and calculates the final size-reduced linear equations. In the second part some theory problems are probed about macro-cell automatically routing for transistor level, and a practical router is developed.Design verification problem needs hierarchy methodology. Because the effect of interconnection has taken in the highest flight, design verification for the interconnection network, for example, only the completed verification for performance of power supply of P/G network can ensure the reliability of chip. General equations group solver methodology cannot satisfy the memory and time in the same time. Using the hierarchy thought, an algorithm, which bases on network partition and equivalent compress by the analyzing the network model correspondence the linear equations group, is proposed. It firstly utilizes the characteristic of layout geometric information to partition the global network into some sub networks. After these sub networks are compressed by Cholesky factorization, the sub networks edge nodes are combined with other nodes.Calculating the final linear equations group, the algorithm can be very effective.Similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard-cell methodology can be divided into two levels: inner standard-cell and among standard-cells. However, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard-cell. Because the router cannot impose the characteristic of the transistors in the standard-cell, it may reduce the performance of the whole chip. In the paper, an automatic macro-cell routing system, which bases on the architecture of three levels: chip, macro-cell and transistor group, is discussed.Firstly a routing problem among transistor groups is brought forward. By analyzing the property of optimized rectangle Steiner tree, an algorithm of approximate rectangle Steiner tree construction is proposed. According to the mutual exclusion relationship among the net ports in the DVCs, the strategy for choosing connection ports is advanced.Wirings of the poly layer are always utilized under the silicon grid technics. To control the macro-cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. The metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized. An algorithm, which is available for BBL structure and can reasonably distribute crossing among multi-nets, is proposed. It can decide the position relationship among wirings of different nets in the routing area.In the entitative routing stage, the macro-cell layout must be compressed for optimization area and time delay. It should be compared beauty with the routing result by manual. An algorithm, which is gridless, variable widths and minimizing layer permutation, is advanced for channel region. The algorithm realizes the goal of minimizing the unconditional via number based on topologic crossing analysi...