Study On Si/SiGe Heterojunction Device

The rapid development of mobile communication, GPS, radar and high speed date process system bring forward much higher demands to semiconductor device's characteristics, such as cut off frequency, power dissipation, and cost. Compared with Si and compound semiconductor device, Si/SiGe heterojunction device can meet the demand with higher performance-cost ratio, so, which have become one of the hot fields in the world. In this paper, based on the research of Si/SiGe heterostructure characteristics, epitaxy technology and physical mechanisms of p-MOSFET and SiGe-HBT, SiGe-p-MOSFET and SiGe-HBT were optimized and fabricated successfully.Firstly, through theoretical analysis and computer aided simulation, optimized design principles for Si/SiGe-p-MOSFET are given, including the choice of gate materials, determination of Ge fraction and profile in SiGe channel, optimization of thickness of gate dioxide and silicon cap layer, and adjustment of threshold voltage. In light of them, SiGe-p-MOSFET sample was designed and fabricated. Measurement indicate that the SiGe-p-MOSFET's (L=2|im) transconductance is 45mS/mm (300K) and 92mS/mm (77K), while in Si pMOSFET, it is 33mS/mm (300 K) and 39mS/mm (77K).At the same time, a simple model of the sheet hole density in 2DHG in Si/SiGe-p-MOSFET is presented. The presence of the first two sub-band energy levels in the quantum well are taken into account but the parasitic channel in Si cap layer is neglected for the time being. Comparison between data simulated by this model and MEDICI indicate that this model is accurate before the parasitic channel is formed. This model can be applied to simulate the threshold voltage, current-voltage and C-V characteristics of Si/SiGe-p-MOSFET in LSI simulation.Secondly, the influence of the base doping profile, base recombination and heteroj unction barrier effect (HBE) on the characteristics of SiGe-HBT were analyzed in detail. A device sample was designed and fabricated. The current gain is 50, and the cut off frequency is 5GHz.About the process, Si/SiGe alloy layers were formed by MBE at 450~550癈, which have proper Ge fraction and doping (B and Sb) profiles needed in device fabrication.IVThe thermal stability was researched in order to determine the process conditions, such as the temperature and time of thermal oxidation, anneal, and so on.Using wet thermal oxidation, a SiOi gate isolator is obtained at 700 ~800℃, 30~150min. The oxidation speed of Si cap layer is much more higher than that of conventional Si, which is mostly because the presence of strain, impurity and the out diffusion of Ge in SiGe channel.At the same time, the gate isolator is formed by PECVD, at 300℃ and a relative low deposition power is used. Before and after raped thermal anneal, the density of interface state is 3.118X 10ncm~2-eV"1 and 1.1 X 1011cm~2-eV~1 respectively.A new layout technique is given and used in our experiment. Through rounding, more than 3 pieces of layouts could be combined together, so that, the number of layout used in experiment could be reduced.