Experimental Study Of Low Temperature Si Process Technology To Prepare Sige Mosfet

As the critical dimension (CD) of the MOSFET has fallen bellow 90nm today, it will be encountered the limit in the next 10¹5 years and bring the crisis to the scaling, which has been the primary way pushing the development of the microelectronics in decades. In searching propellants for the next generation microelectronic devices and integrated circuits, heterostructure has been attracting more and more attentions, which can enhance carrier transport in the MOSFET channel. Because its compatibility with standard silicon technology, silicon germanium (SiGe) is the most promising candidate as either channel material or relaxed virtual substrate for strained-Si CMOS. Grown by Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), nearly fully relaxed SiGe layer can be achieved with threading dislocation density less than 10⁶cm^-2 and thickness of several micrometers .However the composition grading technology has several drawbacks such as the ultra-thick relaxing layer and rough surface which are unfavorable for the subsequent fabrication etc. This disertation focuses on novel techenique for the fabrication of SiGe MOSFET. Instead of UHVCVD, MBE is more favorable for accuratly control of the growth speed, doping concentration and higer device performance. Using 400°C low-temperature Si technique in fabricating strain-Si PMOSFET, the thichness of the relaxed SiGe substrate has been reduced to 400nm. Not only the heat conduction of the divice is improved, but the surface RMS is reduced to 10.2A. Employing the conventional Si technology except for high temperature steps, successful fabrication of SiGe strained Si MOSFET indicates that the LT-Si technique is very helpful in relaxed SiGe epilayer growth. Experiments have shown that higher Ge faction in the virtual substrate will bring higher device performance, which indicates more advantageous of LT Si technique.