Study On The Model Of IC's Defect Spatial Distribution And The Technology Of IC's Fault-Tolerant Design

AbstractThis dissertation airns at discussing the model of defect spatial distribution, IC'sfault-tolerant structures and yield. A large numbers of simulation examples show thernodels and the methods presented in this dissertation are very effective by usingXD-YES simulator (XiDian university held EStimator).The autl1or's main contributions are as fOllowing fFirst, the fozzy degree of each defect is defined according to the position of thedetbct o11 tIle wafbr and the correlative coefficient between a detbct cluster and a defectcluster is defined An effective change-step fuzzy cluster algorithm (CSFCM), which issuitable to partitioning the defects into clusters, is firstly presented in this dissertation'1-lle (listributioIl of tl1e 11ull1ber of clusters oIl tlle 1vafer, x\/hicl1 obeys Poisso11'sdistribution with;. as a parameter, and the distribution of the number of defects in aclLlster, 1vIlicI1 obeys Releigll's distributiOIl with a as a paraIl1eter, are obtained bystatistic and testing the data.The new defect spatial distribution is presented in this dissertation based on thedistribution of the number of clusters on the wafer and the number of defects in a clusterThe negative binomial distribution and the new defect spatial distribution arerespectively used as the defect spatial distribution in the XD-YES simulator when thegiven layouts are simu1ated with XD-YES simulator, The simulation results show thatthe difference between results obtained by the negative binomial distribution and thenew model is small fOr a small area chip, and that the simulation results consistent wellwith testing results, the difference between the results obtained by the negative binomialdistribution and the new tnodel is large fOr a large-area chip, the simulation result usingthe new model is more close to the testing results.A Hopfield network algorithm to solve the allocation of spare rows and columns ina memory array is presented in this dissertation according to the property of the defectarray fixed by spare elements. A large numbers of validated examples indicate that theHopfield network algorithm is very effective to solve the allocation of spare rows andcolumns in a memory array.The Markov chain is used to analyze the yield of the memory array with sparerows and columns according to the change of the number of spare elements. The effectof the defect spatial distribution to the yield of the memory array is taken into account during analysis yield. A comparison of the yield method of Markov抯 chain and the traditional yield methods shows that the Markov抯 chain method has higher precision than traditional method by analyzing a number of examples.As redundancy is added the yield of the memory goes up, but the area of each chip also increases. This in turn reduces the number of chips that can be obtained from a wafer. The influence of chip area variation on yield is synthetically considered in this dissertation when the two-level hierarchical redundancy added into the chips. The rule, which optimally partitions the given multimegabit RAM抯 into modules to make the RAM抯 yield be optimal, is given in this paper.Finally, an optimal allocation model of the sub-processing-element (sub-PE) level redundancy is developed by genetic algorithm. The average defect density D and the support circuit parameterS are considered in the allocation model to accurately analyze the element yield. Under the condition of the given area constraint, simulation results indicate that the number of the optimal redundant sub-circuit added into a PE and the PE抯 yield decrease for any given average defect density D as S increases; the number of the optimal redundant sub-circuit increases, while the optimal yield of the PE decreases for any given support circuit area parameter S as D increases.