Research On Design Technology Of FPGA Hardware Component Based On Meta-Component

With the improvement of integration, the number of transistors inside the chip is increasing. As the design's complexity of integrated circuit is getting higher and higher, computer aided design technology has become increasingly important. Due to the hardware parallel processing based on spatial characteristics and programmable, FPGA has been widely used in different areas. Traditionally FPGA design needs to go through logic synthesis, mapping, packing, placement and routing processing stages, and the algorithms for different stages of design flow become research focus. Combined with the research of the National High-Tech Research and Development Program of China (863 program)"Research of Reconfigurable Router and its Components"in information technology field, this dissertation mainly studies the design technology in view of meta-component and pipe line design characteristic of FPGA hardware component. The main works and contributions in this paper are outlined as follows:As FPGA design cycle is long, in order to accelerate FPGA hardware component development progress, a new FPGA development flow is proposed. Meta-components are extracted based on hardware component structure analysing. As the block level netlist format of a specific type of FPGA is fixed, which can used directly, the hardware description language level netlist of meta-component can be transformed into block level netlist by carrying on logic synthesis, mapping and packing in advance, which can be called from its library directly in hardware component designing.In order to guarantee that the Critical Path Delay (CPD) of sequential circuits shall not exceed design clock cycle, the re-synthesis algorithm in technology mapping step discards all the mapping process which increases path delay. A sequential re-synthesis algorithm based on slack parameters is proposed. The increasing delay is compensated by slack, restriction on the scope of the mapping is broken by local retiming and the requirement of clock cycle is guaranteed by global retiming. Experimental results show that the proposed algorithm can improve the efficiency of area optimization of re-synthesis algorithm under the restriction of design clock cycle.In order to improve routability in FPGA design packing step, a packing algorithm based on analysis of wire absorption and port occupancy is proposed. A routability driven function is defined based on analysis of influence of packing on wire absorption and port occupancy. Path delay requirements are ensured by absorbing critical paths and area-efficiency is improved by hill-climbing. Experimental results show that by absorbing more wires and decreasing occupying ports, the proposed algorithm can improve routability efficiently. In addition, the CPD also can be decreased by integrating delay driven parameter. In traditional simulated annealing algorithm in FPGA design placement step, the timing quality of one layout is measured by timing cost which is calculated based on its CPD. In some circumstances, the timing cost and the layout transformation does not match. A simulated annealing FPGA placement algorithm based on unified CPD is proposed which proves that the timing cost calculated based on unified CPD can match layout transformation in all circumstances, the probability of accepting a move which exceeding CPD is reduced by introducing punishment factor, benchmark standard of punishment factor is setting according to impact on convergence of CPD. Experimental results show that the proposed algorithm can decrease CPD effectively.As the searching space is large, simulated annealing needs more operation time and does not adapt to large-scale circuit's placement. A twice placement scheme is proposed according to the characteristics that the internal logic unit blocks in meta-component are closely related and ideally layout in adjacent position. A region distribution technology for meta-component initial placement is proposed. This technology first carries on wire optimization by using quadratic method, and then carries on routability optimization by partitioning meta-component set in a way which ensures balanced length-width ratio of distributed region for meta-component. As to block placement in distributed area for meta-components, the simulated annealing layout process can be accelerated by setting a lower annealing temperature and a smaller moving range. Experimental results show that the proposed twice placement scheme is effective.