On-Chip High Performance Embedded Computing-Soft Baseband Application Parallel Processing Model & Architecture

High Performance Embedded Computing (HPEC) including wireless computing is ubiquitous in society life, industry application and military technology. The computing complexity, power budget and real-time constraint of different HPEC applications are varied and strengthening, the morden HPEC is undergoing the transformation from the traditional HPEC based on general Digital Signal Processor and general high performance embedded processor to domain specific HPEC. The soft baseband, which is resulting from the evolution of wireless protocols and the requirements of muti-mode communication, is one of the main driving applications of domain specific HPEC. The architecture design of On-Chip High Performance Embedded Computing (OCHPEC) for software baseband is being challenged for its high computing complexity, high performance power ratio constraint and high real-time constraint, especially when MIMO-OFDM baseband system is involved. Besides, to meeting the computing requirements of the evoluting wireless protocols is also an issue of architecture design of OCHPEC for soft baseband.Based on the analysis of the MIMO-OFDM system model, this dissertation focuses on the following research points:soft baseband application parallel processing model for MIMO-OFDM, Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture, multi-pattern multi-domain conflict-free parallel memory architecture, Low Desity Parity Check (LDPC) code decoding algorithm/accelerator and Reed Solomon code decoding algorithm/accelerator. The key contributions are summarized as follows.A. The application parallel processing model for MIMO-OFDM based soft baseband is introduced, including data stream model, space-time 2-dimension data level parallel model and atom operaion model. The data stream model describes the data stream dependency relationship between the baseband tasks, and the stream quantifing model; space-time 2-dimension data level parallel model describes the data level parallelism of the baseband tasks; atom operaion model describes the specific operaion sequences of MIMO-OFDM baseband tasks. A typical MIMO-OFDM baseband system is analyzed based on this application parallel processing model, the complexity evolution of the kernel operaion, the parallelism evolution of the atom operaions and the stream flux evolution of the tasks are showed.B. Domain specific programmable process unit is proposed and researched. The proposed programmable process unit adopts scalar and vector hybrid processing technique. It introduces VLIW and SIMD to support the varied computing patterns in target applications. It introduces general and application specific inter-cluster data exchange network to accerating the atom operaion when SIMD technique is used. ESL methodology and tools are used to model and implement the domain specific programmable process unit. Some typical algorithms are used for evaluating the performance of the domain specific programmable process unit. The results shows the proposed domain specific programmable process unit is more efficient than others in the kernel algorithms of wireless communicationC. A domain specific memory organization model is proposed after analyzing of main memory access patterns. Based on the memory organization model, a Multi-Pattern and Multi-Domain conflict free Parallel Memory Architecture (MPMD-PMA) model for the main memory access patterns is proposed. The implementation detail and the pipelined case study of MPMD-PMA is done based on the proposed domain specific programmable PE, and the memory access simulation experiments have been done in the behavior simulator. The implementation results show the expansibility of MPMD-PMA is equivalent with general PMA; and the simulation results show the performance speedup of MPMD-PMA over general PMA in soft baseband memory access patterns is significant.D. RMP-Min-Sum decoding algorithm for LDPC codes, which is the newest FEC code, is proposed to reduce the LDPC decoding complexity. RMP-Min-Sum introduces the Row Message Passage pattern to reduce the decoding iterations, and Min-Sum algorithm to reduce the complexity of the kernel operations. The simulation results show the application value of RMP-Min-Sum decoding algorithm is significant. The hardware cost of the RMP-Min-Sum decoding implementation in software has evaluated, and the results show it is not a high efficient solution for long frame structure LDPC code. Then, the parallel accelerator architecture based on RMP-Min-Sum decoding algorithm for eIRA-LDPC code is proposed, and the case study of DVB-S2 LDPC decoder is showed. The results show hardware cost of the parallel accelerator based on RMP-Min-Sum decoding is less than other LDPC decoder.E. TD-iBM:a Key Equation Solver (KES) algorithm for supporting RS decoding balanced macro-pipeline architecture is proposed. It adopts time division scheduling of the Galois Field multipliers in iBM based KES algorithm to reduce the complexity of KES and balance the macro-pipeline. Decoding accelerator architecture for RS (255,223) and its truncation codes is proposed based on TD-iBM algorithm. The results show the decoding accelerator based on TD-iBM algorithm is an area-efficient decoding accelerator.F. Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture and prototype are proposed based on the programmable process unit and some FEC accelerators. In PH-MPSoC architecture, Software Controlling -Time Division Multiplexing bus (SC-TDM bus) is introduced to offer the predictable interconnection timing. SC-TDM bus offer the design time bus scheduling scheme with little hardware cost, and different bus scheduling patterns can be introduced by programmer. Besides, the design time predictable bus scheduling scheme can be used to reduce the power cost of the interconnection. The PH-MPSoC prototype is proposed, and optimized prototype implementation is designed for the simplified MIMO-OFDM baseband system pipeline mapping scheme.In summary, this dissertation investigates soft baseband application parallel processing model, domain specific MPSoC architecture and implementation technology, high efficient parallel memory architecture and FEC decoding algorithm and accelerator architecture. The contributions of this dissertation are useful in driving the development of the OCHEPC for soft baseband processing.