Research On High Productivity I/O Architecture And Implementing Technology For Multi-Core Microprocessor Chip

Microprocessor works as the brain and engine of modern high-end computing systems, Human needs for computing power, novel architecture and new techniques are driving the continuous improvement of microprocessor's performance. PSoC(Parallel System on Chip)has been the main form of high performance microprocessor's architecture. With the development of computer technology, the high productivity is presented to solve many problems currently existed in the field of high performance computing. These problems mainly include the practicability, programmability and lower cost, portability and robustness.This dissertation is devoted to study high productivity I/O architecture and implementing technology of multi core microprocessor. This paper has done so from the following aspects: memory coherency model including I/O, optimization of I/O performance, hardware enhancement I/O virtualization, low power optimization and error tolerance design for I/O system. Several novel approaches are proposed, such as solutions for easily programming, high performance, usability, low power and reliability, which are the key techniques of a high productivity I/O system.The main contributions are as follows.1. Generalized Coherency Models Including I/O for Multi-core architecture are proposedThis dissertation is devoted to study I/O coherence problem. The reason and solution of I/O coherence are analyzed and proposed in terms of time and space based on product-customer model. The causes and solution of I/O coherence for remote I/O access in SMP system based on multi processors interconnection are analyzed and put forward, too. I/O coherence problem is incorporated into the same framework of memory coherence problem, which is described from the point of relationship among cores, I/O and memory. The generalized coherence models including I/O for multi core architecture are proposed, experimental results show the models can not only provide a simple and efficient programming interface, but also improve the I/O performance.2. Optimization method for I/O coherency maintaining is proposedThis dissertation is devoted to study optimization method for I/O coherency maintaining. The characteristics of I/O data are analyzed, and eight kinds of I/O data characteristics are summarized, as well as the impact on I/O coherency maintaining is analyzed to direct optimization of I/O coherency maintaining. In this dissertation, I/O Cache is organized based on Cache partitioning method to optimize I/O performance. Dynamic Self-selected Hybrid I/O Coherence Method(DSHIOCM) is proposed to optimize the performance of local and remote I/O access. Experimental results show that DSHIOCM can significantly improve the performance of different complicated I/O applications. Enhanced Synchronization I/O Coherence Maintaining method and Boundary Splitting I/O Coherence Maintaining method are proposed to optimize remote I/O access for traditional I/O applications and user level communication applications. Experimental results show that these methods can improve the I/O performance of remote I/O access effectively.3. Optimization methods for Hardware Enhanced I/O Virtualization are proposedOptimization methods for DMA remapping and interrupt redirecting which are the key techniques of hardware enhancement I/O virtualization are studied in this dissertation. An IOTSB Cache Management Method based on Hints (IOTCMBH) and an Invalidation Method based on Invalidation Queue (IMBINQ) is proposed to optimize DMA remapping. A multi-levels controlled interrupt model and a flexible interrupt redirecting method are proposed. Experimental results show that these optimization methods can support I/O virtualization high efficiently at a low cost.4. Low power optimization and error tolerance design methods are proposedPower optimization method and reliability enhancement method of multi-core microprocessor are proposed in this dissertation. Design guidelines for architecture are proposed to direct low power and error tolerance design. Data Drivering Refresh with Enhancing Multi-bit Error-Correcting method is proposed to optimize the refresh power of I/O Cache based on eDRAM. Experimental results show this method can reduce refresh power efficiently with very low performance cost. Low power optimization based on Cache organization and hybrid low power mode for I/O Cache based on SRAM is proposed. Experimental results show the method can improve leakage power and dynamic power efficiently. Prospective Dynamic Frequency Scale with Clock Gating Method is proposed to optimize dynamic power of I/O logic. Experimental results show this method can reduce dynamic power significantly with very low performance cost. A soft scrub method for multi-core processor is proposed to tolerance soft error. Experimental results demonstrate that this technique is highly and can be used in the design and implementation of soft error tolerant multi core microprocessors. I/O coherence maintaining based on retransmission is proposed to improve reliability of the I/O coherence protocol. Experimental results demonstrate that this method can enhance the robustness of I/O coherence protocol.