Research For Buffer Management Problem Of Hybrid Memory Architecture Based On Phase Change Memory

With the rapid development of computer technology, there has been an explosive growth of the data scale in networks, data centers, high-performance computing and other areas. Due to the growth of data scale, the requirement of data access speed become more and more urgent. Hard Disk is hard to improve its I/O speed because of its mechanical structure, and is difficult to meet the need of access speed for large-scale data. To solve this problem, the idea of using large-capacity main memory to store important data has been presented, and has been valued in academia and industry. This brings the urgent need of lagre-capacity main memory. However, as the mainstream main memory media, DRAM has some problems for building large-capacity main memory because of its disadvantages. the storage density of DRAM is difficult to improve, so the average stroage unit price of DRAM is much expensive than Hard disk. In addition, DRAM has high energy consumption, and its energy consumption increases in proportion with its capacity. Therefore, the cost of building a DRAM large-capacity main memory system is very high.Phase change memory(PCM) is a new storage technology for main memory based on chalcogen media, it make use of the characteristic of chalcogen media, the difference of resistance in different states, to store data. Phase change memory has the following characteristics:non mechanical parts, byte-address, nonvolatile, no idle power, high storage density, and low latency. Compared with the DRAM, phase change memory has advantages of nonvolatile, storage density and power consumption. So PCM is considered as the most promising next-generation main memory to substituted DRAM. How to merge PCM into current computer architecture has become a hotspot in academia.However, two problems of PCM make it difficult to totally replace DRAM in current computer systems. First, the write latency of PCM is about 7 to 20 times slower than that of DRAM. Second, PCM has a worn-out problem because each PCM cell has limited write endurance. A more practical way to utilize PCM in memory architectures is to use PCM and DRAM together as the same level memory to construct a hybrid memory architecture.Since hybrid memory architecture has two different storage media, traditional DRAM-based data management technologies do not fit for hybrid memory. Among these technologies, buffer management technology is of great importance and directly related to the performance of memory. For DRAM-only memory, hit ratio is the key metric to buffer management algorithms. But for hybrid memory, we should not only consider hit ratio but also consider how to manage data in heterogeneous memories to reduce PCM writes and improve overall performance.This paper focus on the research of buffer management technology for hybrid memory architecture that uses DRAM and PCM as same-level memory. The key problem is how to reduce PCM write count while maintaining the hit ratio. Based on traditional buffer management algorithm, this paper present a series of hybrid memory buffer management algorithm that can effciently reduces PCM writes without hit ratio degraduation.First, this paper introduce the technical background of PCM and summarize the research of different types of PCM memory architectures and data management technologies based on these architectures. Specially,this paper analyze the existing works on hybrid memory buffer management algorithm and point out the problems.Then, based on LRU algorithm, this paper modify the page loading way of LRU algorithm to reduce PCM writes while maintain hit ratio; Based on the modified LRU algorithm, to solve the problem that pages in PCM become write-intensive, this paper design a page exchange mechanism between PCM and DRAM and merge it into the algorithm; finally, this paper analyze the impact of page replacement on PCM writes, and present a new page replacement algorithm that consider balancing page replacement between PCM and DRAM.The main contributions of the paper include the following aspects.(1) we propose an "migration during replacement" strategy and LRU-based hybrid memory buffer management algorithm MHR-LRU that adopts this strategy. When page replacement occurs, MHR-LRU load requested pages on the suitable memory device by performing page migration between PCM and DRAM according to the type of page request. By doing so MHR-LRU reduces PCM writes from loading pages and reduces write requests on PCM in future while maintaing hit ratio, improves the overall performance.(2) Based on MHR-LRU algorithm, in order to solve the problem that pages in PCM become write-intensive, we propose a modified algorithm MWQ-LRU that adopts a page exchange mechanism betwen DRAM and PCM. MWQ-LRU consider page’s write frequency and recent written time to judge if a page in PCM become a write-intensive page, and exchange the write-intensive page in PCM with a write-nonintensive page in DRAM. MWQ-LRU can keep write-intensive pages in DRAM while maintaining hit ratio to achieve additional performance.(3) In order to solve the problem that existing work reduce PCM writes inefficiently under read-intensive workloads, we point out that the main part of PCM writes is from page replacement under read-intensive workloads but existing works do not consider the impact of page replacement on PCM writes. We propose a new CLOCK-based hybrid memory buffer management algorithm D-CLOCK that consider the impact of page replacement. The algorithm can reduce the impact of page replacement on PCM writes while maintaining hit ratio, and efficiently reduce totaly PCM write count under read-intensive workloads.