DDR-NVRAM Memory Page Migration Mechanism With CPU Bypass

With the rapid development of integrated circuits,complex instruction sets can no longer meet the requirements in terms of design time and cost.A new type of instruction set architecture,RISC-V,has attracted everyone's attention.Its design is simple and generous,and has strong scalability.However,there are few researches and explorations on the memory control part of the new chip.The memory controller has a great influence on the overall performance of the computer,and the memory control of the new chip will affect the development of subsequent memory and the overall performance of the computer.At the same time,in terms of memory,research on heterogeneous memory is gradually deepening.Combining the read and write advantages of Dynamic Random Access Memory(DRAM)with the large-capacity storage of Non-volatile Memory(NVM)can effectively improve the performance and service life of the memory system.Combining these two points,low RISC can be used as a platform to design a heterogeneous memory hotspot data page migration mechanism that implements CPU bypass.The functional modules of the page migration mechanism mainly include FIFO buffer,control MIG reading and writing module,address range division and monitoring delay module.1)Through the FIFO buffer,the data migration channel between DDR-NVM can be realized,reducing the preemption of the memory channel to improve the system performance.2)Controlling the MIG reading and writing module is to replace the CPU to send memory access instructions to complete data reading and writing.The state machine is designed according to the AXI4 protocol,and the state jump is controlled through signal changes and reading and writing counting.The memory controller controls the data migration in the memory to ensure that the CPU is insensitive.3)The address range division and monitoring delay module can simulate a mixed heterogeneous memory system.Divide the address range of the DDR on the board,one part is used as DRAM,and the other part is used as NVM.Use the delay module for data delay processing,simulate the NVM read and write characteristics,and solve the problem of no commercial NVM available for experimentation.Provide environmental support for other modules.A total of 6 sets of data tests were conducted in the experiment,and the following conclusions were drawn: 1)When the ratio of read and write accesses is the same,the more data accesses within the NVM range,the more obvious the system performance improves.2)The write operation has a greater impact on system performance.When the read ratio is large,the system performance is increased by an average of 37.1%;when the write ratio is large,the system performance is increased by an average of 44.2%.3)Compared with the native low RISC system,the system performance with the hybrid memory controller is increased by an average of 43.0%.