Analysis And Optimization Of Electrical Transmission Properties For Through Silicon Via(TSV)

With the feature size of integrated circuits continuously scaling down, the problems that restrict the development of two-dimensional integrated circuits have become more and more serious. When the resource in planar space is not capable to meet the requirements of the rapid development of integrated circuits, more challenges have been posed to Moore’s Law. The through silicon via (TSV)-based three-dimensional integrated circuits (3D ICs) are emerging as one of the effective solutions to preserve Moore’s Law, as they can improve the interconnect performance and enhance the integration level by providing the vertical TSV-interconnects between stacked chips. TSV-based 3D ICs have bright prospects in terms of application as they have many advantages. However, there still exists some issues which need to be explored, including the accurate models to analyze and predict the performance of 3D ICs, the design methods to optimize the performance of 3D ICs, the effective ways to establish the power delivery models of 3D ICs, and the feasible techniques to achieve low power applications. This paper studies these issues as mentioned above, and the results obtained are listed below:1. An impedance-level model of coupling channel between adjacent TSVs based on the two-port network is proposed, which can be used to describe the TSV-TSV crosstalk effect. By converting the impedance parameters of the model into ABCD matrix, the formula of coupling coefficient is derived, which can be used to estimate the crosstalk level from TSV-TSV in the early design stage. By comparing with 3D full-wave electromagnetic simulation software ANSYS HFSS, the analytical results show a good correlation with simulation results up to 20 GHz, and the changing trend of the coupling coefficient due to the variation of design parameters has also been captured well by the proposed formula, thus validating the accuracy of the proposed formula.2. The crosstalk effect between TSV and interconnects in the re-distribution layer (RDL) is studied, and the factors which influence the coupling capacitance between TSV and RDL are analyzed. The work can help designers to optimize physical layout and improve the signal integrity of 3D ICs. The research shows that:with the mumble of RDLs which are placed beside TSV increasing, the coupling capacitance between TSV and the corresponding RDL decreases, while crosstalk between the farmost RDL and TSV is not the minimum one; when there is one RDL placed beside TSV, the coupling capacitance existed in different small units of RDL is not uniformly distributed; when there are two signal RDLs placed beside TSV simultaneously, the TSV is severely effected. However, by adjusting the size of TSV (to decrease the TSV diameter or to increase the TSV height), the capability of TSV to avoid the RDL interference can be enhanced.3. The discharging path which exists between the TSV and the silicon substrate is proposed. Through the theoretical analysis and simulating validation, an optimization design method is obtained that the crosstalk noise on the victim TSV can be reduced by lowering the impedance of discharging path, which can help designers to optimize the performance of 3D ICs. Conventional models consider the silicon substrate which covers around the TSV is in a state of floating. However, the silicon conductivity (typically as 10 S/m) is non-negligible; otherwise, the crosstalk noise on the victim will be overestimated. For the proposed discharging model, the frequency-dependent characteristics of its parameters are firstly analyzed, and then the equivalent expressions are obtained. By comparing with the 3D quasi-static electromagneitc simulation software ANSYS Q3D, the accuracy of the equivalent expressions obtained is validated. Moreover, by varying the doping concentration of silicon substrate, the impedance of discharging path is adjusted. And through the simulation results, the method of lowering the impedance of discharging path to mitigate the crosstalk noise on the victim TSV is verified.4. The power delivery of 3D ICs is studied, and the 3D power distribution network (PDN) model is established. The impact of number of TSVs and the stacked chips on the IR drop of 3D PDN is firstly discussed, and then the current density distribution inside a TSV is analyzed. Through experimental results, the conclusion is made:with the number of TSV which connects the stacked chip increasing, the IR drop of each chip is improved; with the number of stacked chips increasing, the IR drop of each chip is deteriorated; with the uniformity of the current density distribution inside a TSV enhancing, the IR drop of TSV increases, and thus has a negative impact on the signal integrity of 3D ICs.5. An on-chip switched-capacitor power converter is proposed, which enables different chips or different functional blocks in 3D ICs to operate with the ideal speed according to the performance requirement, thus achieving the low power design of 3D ICs. The converter has a multiple output structure, which can provide voltages for full-speed operation (VDD, super-threshold), low power operation (2VDD/3, near-threshold), and ultralow power operation (VDD/3, sub-threshold). Using the multiple supply voltages provided by the proposed converter, different chips or different functional blocks in 3D ICs can operate in optimal power modes, and avoids continuously operating at full speed with single full VDD.This paper has important reference value and academic significance in several aspects of TSV-based 3D ICs, including the analysis of electrical characteristics, the study of performace optimization, the research of power delivery, and the design of acheving low power application.