Design Of High-speed SG DMA Controller For TTE Terminal

With the promotion of smart mobile devices,network application scenarios are bound to show diversified characteristics.In some scenarios,for example,when ground radar transmits telemetry data to a spacecraft,it not only requires the network to have extremely high data throughput,but also has extremely high requirements on the jitter and delay of data transmission in the network.The network that carries telemetry data needs to have the characteristics of high reliability,strong real-time performance,and low jitter,while traditional Ethernet obviously does not have the above characteristics.In this context,because TTE has both the flexibility of traditional Ethernet and the certainty of time-triggered protocol,it provides a strong guarantee for the establishment of a highly reliable network.Finally,the TTE network has become the preferred solution in the above-mentioned scenarios.At present,there are two main issues that the PCIe interface-based gigabit TTE terminal pays attention to.The first problem is the performance of PCIe.Because the theoretical bandwidth can only reach gigabit,the TTE terminal cannot be used in high-speed data transmission scenarios.The second problem is that PCIe introduces a large amount of delay and jitter when processing small packets,which will reduce the certainty of the TTE network.This article will study the first problem,develop a DMA controller based on Scatter-Gather technology,and combine it with time-triggered Ethernet to design and implement a 10 Gigabit TTE terminal based on PCIe interface.This article first introduces the research background and current research status of PCIe protocol,time-triggered Ethernet and DMA technology at home and abroad.Secondly,the basic knowledge of TTE network,DMA technology and PCIe protocol is introduced,and the TTE terminal is explained as a whole from the perspectives of design requirements,overall scheme,and data receiving and dispatching process.Third,the study introduces the overall design architecture of the SGDMA controller in the TTE terminal,and discuss in detail the function and design ideas of each sub-module from the perspective of interface signals and operating procedures.Fourth,the paper builds a simulation model and FPGA board-level test environment for the SGDMA controller.This article uses the simulation model to perform functional simulation verification,and uses the FPGA to test the performance upper limit of the SGDMA controller.Fifth,the article draws a conclusion:the peak read and write rates of the SG DMA controller are 13.2Gbps and 13.47 Gbps,which can fully meet the bandwidth requirements of the 10 Gigabit TTE terminal.