Research On Key Techniques Of PCI Express3.0 DMA Controller Based On FPGA

With the development of technology,the requirement of the signal transmission bandwidth of satellites and radar IF(Intermediate Frequency)signal processing systems becomes increasingly higher.PCI Express3.0 has been widely used in the field of high-speed data transmission due to its excellent performance.The current implementations employ the integrated PCI Express3.0 hardcores.Although this method realizes parts of the function of PCI Express3.0,its advantages in transmission bandwidth performance will be limited when used directly.It is important to study an improved transmission scheme of PCI Express3.0 based on FPGA by adding Direct Memory Access(DMA)controller for enhancing the data transfer bandwidth of PCI Express3.0.Therefore,this thesis focuses on the key technologies of PCI Express3.0 DMA controller.The main research work of this thesis is as follows:This thesis proposes the overall architecture of PCI Express3.0 DMA controller,and analyzes the function of each module.This thesis introduces the concept of the protocol and the DMA controller,studies the Xilinx's PCI Express3.0 hardcores,and summarizes the main problems in the established methods.This thesis analyzes and proposes the solution for the key technologies and difficulties in the design of PCI Express3.0 DMA controller.(a)This thesis proposes a Read Buffer method to solve the chaotic sequence of DMA read completion packet.(b)Aiming at the integrity of the data caused by MSI interrupt and the hidden trouble,the new MSI configuration process is adopted.(c)Aiming at the problem of low efficiency of common DMA method,this thesis proposes Scatter-Gather DMA in DMA controller.This thesis verifies the design of PCI Express3.0 DMA controller.By building the test platform,the thesis verifies the functionality,transmission speed and stability of PCI Express3.0 DMA controller on a practical FPGA platform.Measured results show that the proposed implementation of the DMA controller meets the given design specifications.When setting the DMA transfer size as 16 MB,the x4 Lane DMA read/write speed can stably reach 1900 MBytes/s,which can meet the bandwidth requirements of an ultra high-speed data transmission system.