The Design And Implement Of Vector Memory To Support Gather/Scatter

With the rapid development of digital signal processor(DSP)applications,how to improve DSP computing performance is facing new challenges.The SIMD architecture has exploited the data-level parallelism of applications and has acquired higher peak performance with lower hardware and power budgets,which has become the mainstream of high-performance DSPs.SIMD DSPs often support regular data memory access with contiguous or equal address strides,but could not well support irregular data accesses that exist widely in scientific computation and engineering applications.The irregular access makes SIMD DSP memory bandwidth efficiency decreased which reduces the overall computing performance.Gather/Scatter memory access technology can alleviate this problem effectively.V-DSP is a high-performance vector DSP core developed by the research group.According to the requirement of its vector access,this paper designs a Gather/Scatter vector memory based on its previous double vector Load/Store and implements irregular data Vector memory,which extends the use range of vector memory access and improves the bandwidth efficiency.The main work and innovations of this paper are summarized as follows :1?Based on analyzing the characteristics of random data access,this paper puts forward an design of SIMD conflict buffer array to buffer the vector memory access requests failed in the arbitration and ensure the pipeline executing.The quantitative models of Gather/Scatter memory allocation and the memory access confliction are established.The optimal size of the conflict buffer with different SIMD width is presented,which could reduce the hardware overhead effectively.2?According to the characteristics of the wide SIMD vector memory access of VDSP,the overall structure of Gather/Scatter vector memory(GSVM)is designed.Dedicated Gather/Scatter memory addressing instructions and vector address register file are designed.3?On the basis of supporting its two Load/Store vector memory access pipelines,the Gather/Scatter memory access pipeline is designed and implemented,including instruction decode,address calculation,memory access arbitration and data synchronization.The design uses the method of separating the vector memory access to different banks and resolves the Gathe/Scatter access conflicts of 16 VPEs effectively,which increases the bandwidth and efficiency of irregular data memory accesses.4?The RTL code of GSVM is designeded.Module-level verification platform based on SystemVerilog is built,and module-level verification is completed with the help of assertions.The code coverage of the verification meets the design goals.5?The result of running multiple sets of sparse matrix test sets has shown that the vector memory supporting Gather/Scatter memory access could improve system performance significantly.Compared to the conventional scalar memory access,GSVM acquires 2 ~ 3 times speedup.Finally,based on the 40 nm process and timing constraints of 0.54 ns,the logic synthesize of GSVM has been finished.The result has shown that the timing constraint is met,the total area increases 22%.