Design And Implementation Of PCIe Bus Controller For TTE End System Adapter Card

With the development of information technology,real-time network transmission scenarios,such as network transmission in the fields of unmanned driving and aerospace,bring new challenges and demands to traditional networks which based on event triggering.Therefore,real-time network protocols have become the hot research in various countries.The Time-Triggered Ethernet stands out in the fierce competition because it combines traditional Ethernet,IEEE 1588v2 time synchronization technology,time-triggered protocol,rate-constrained traffic flow transmission and guaranteed transmission.TTE will combine trigger time certainty and high real-time performance with the dynamics and “best effort” of traditional Ethernet to support a highly reliable computer network.The TTE system consists of the TTE switch and the TTE end system.The TTE end system which mainly composed of the end system adapter card and the end system host acts as a key device for the TTE end system,and it implements the functions of data transmission & reception of the TT,ET services and time synchronization.The user data which encapsulated into the TT and ET services in the end system host transmits to the end system adapter card through the PCIe bus interface,and the Ethernet frame parsing and data delivery processing are performed on the end system adapter card;The TT and BE services which stored in the card are uploaded to the end system host according to the service priority.The research content of this paper is the design and implementation technology of the PCIe bus controller for the TTE end system adapter card.This paper firstly introduces the research background of TTE system and the related introduction of TTE and PCIe.Secondly,the design requirements of PCIe bus controller are introduced,then focus on the PCIe structure and data receiving & sending process.Thirdly,the design and implementation of the PCIe bus controller in the TTE end system adapter card are introduced particularly.Here are core modules: transmit control engine is mainly responsible for the encapsulation of the PIO read completion packet,the DMA read request packet and the DMA write request packet,and the receive control engine is mainly responsible for the decapsulation of the PIO read request packet,PIO write request packet and DMA read completion packet,the data storage module is mainly responsible for data storage of DMA read completion packets which are in out-of-order Tag,the data combination module is mainly responsible for encapsulating uplink data into DMA write request packet,the interrupt processing-control module is primarily responsible for MSI or INT-x interrupt timing.Finally,the PCIe bus controller is simulation analysis and board-level test,the problems encountered during the test and the solutions are summarized indetail.The board level test shows that the PCIe bus controller designed in this paper can meet the demand of TT and ET service data transmission between the TTE end system host and the TTE end system adapter card.