| With the advent of the era of big data,people's demand for large capacity storage and high bandwidth is increasing,which brings new challenges to the performance of USB interface.Since the first generation USB interface-USB1.0 was came out in 1996,USB interface technology has gained rapid development after more than 20 years of development.USB3.0 is the current version of the high-speed serial bus interface that is widely used,which with a significant performance improvement over the previous versions.The transmission speed of USB3.0 is up to 5Gbps,and it has the advantages of good downward compatibility,flexible connection,independent power supply and low power consumption mode support.It is widely used in computer,smart phone,digital set-top box,wearable device and smart home.In recent years,USB3.0 technology has become mature,but there are not many manufacturers with independent USB3.0IP property rights in China.Therefore,it is of practical significance to design and implement USB3.0 chip at present.The purpose of this paper is to design the physical layer digital circuit conforming to the requirements of USB3.0 protocol specification,and adopt the forward design idea: Based on the design and analysis of USB3.0 physical layer architecture,RTL design is implemented.VCS and Verdi software are used for waveform debugging,the function verification is realized,and function points are analyzed.On this basis,synthesize the digital circuit.Finally,the FPGA verification platform is built to realize the board-level verification of the designed digital circuit.The comprehensive report and the verification results show that the designed digital circuit conforms to the protocol specification.The innovation of the design is reflected in the following aspects: firstly,different from the traditional USB3.0 physical layer digital circuit which only processes 8b/10 b data,this design supports processing 16b/20 b data under 250 MHZ system clock.Secondly,a new 8b/10 b encoding and decoding method is adopted to obtain the output signal through this module with only one beat.Compared with the traditional lookup table design method and multi-stage pipeline design method,the resource consumption is smaller and the data processing efficiency is higher.Thirdly,the elastic buffer circuit can support two modes: normal half-full and flow control.Compared with the single mode elastic buffer,this method has good compatibility and portability.This paper mainly includes the following aspects:(1)In-depth study of the USB3.0 specification standards to determine the design indicators.According to the functional requirements of USB3.0,a feasible USB3.0 physical layer digital circuit architecture was proposed.(2)Verilog hardware description language is used to realize the design of USB3.0 physical digital circuit,including: sending channel,receiving channel,and loopback circuit.The design strategy is used to optimize the circuit module,and the digital circuit is verified and simulated.The verification results show that the designed digital circuit can realize the data transmission with a bit width of 16/20 bit at the clock frequency of 250 MHZ,and meets the functional requirements of the protocol.(3)Using TSMC 12 nm FFC process logic synthesis library,the designed circuit was logically synthesized by Design Complier software.According to the comprehensive analysis report,the digital circuit can run stably at 250 MHZ frequency,the occupied area is about 960.6758um2,which is 20% less than expected,and the power consumption is up to 51.8571 uw.(4)Based on VU440 series FPGA development board developed by xilinx company,a hardware verification platform was built.he board level verification of USB3.0 physical layer digital circuit is realized,and the results show that the digital circuit design meets the expectation. |
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