A Study On Low Latency Technology Of PCIe Physical Layer

With the development of the PCIe protocol,the product speed of the PCIe interface is getting faster and faster,but there are still some latencys in the data transmission process,so reducing the latency of the PCIe interface has become a key subject of current research.Therefore,in response to the above problems,based on the in-depth analysis of the physical layer sending logic and receiving logic,the scrambling module and the elastic buffer were optimized to reduce the latency of PCIe interface,functional simulation and FPGA prototype verification were also carried out.The main contents include:(1)In the scrambling module,two methods were used in design.On the one hand,a common parallel scrambling was used to design a 16-bit scrambler and descrambler.The scrambling sequence generation sub-module and data processing sub-module were designed respectively.On the other hand,the scrambling sequence generation process was simplified,and the calculated scrambling sequence was stored in the ROM in advance.Through the combination of parallel scrambling and memory-based scrambling,complicated combinatorial logic operations were avoided.At the same time,the scrambling module were optimized through two-stage pipeline technology.The firststage pipeline was used to generate the scrambling sequence,and the other-stage pipeline was used to scramble the data.The latency was reduced by 50%,the process of scrambling was speeded up.(2)In the elastic buffer,two design methods were also used for design.The depth of the elastic buffer is generally set to 8.Considering that the link width of most PCIe devices is greater than 1,an elastic buffer with depth of 6 was designed.Both elastic buffers were designed in a normally half-full mode.In the elastic buffer with a depth of6,the conversion part of the binary code and the gray code were reorganized to ensure that the implementation was relatively simple,and the other modules were changed accordingly.By reducing the depth of the elastic buffer,theoretically the processing delay of data packets was reduced by 25%.(3)The functional simulation and FPGA prototype verification were carried out for the scrambling module and elastic buffer.By comparing the simulation waveforms and expected output responses of the modules under different excitation signals,it was found that these modules could correctly implement their functions.During FPGA verification,the exciter was designed according to various data packet structures combined with physical layer functions.Through sampling and observing the signal data of FPGA,it was also shown that each key module could complete the data transmission according to the protocol requirements.Finally,by analyzing the timing results,it is concluded that the latency of the scrambling module after the optimization of the memory scrambling code was reduced compared with the unoptimized module.In this thesis,the scrambling module and elastic buffer were optimized and designed,both simulation and board-level verification operated correctly,and it could be useful in reducing the PCIe latency for some engineering practical applicaiton.