| USB3.0 provides a standard interface for the connection of PC with various equipment. With features of backward compatibility, high speed, stability, plug and play, it is widely recognized and popularized in the market. It is widely applied to the fields of electronic communications, optical fiber transmission, and image acquisition.In recent years, with the increasing demand for high speed data transmission, traditional serial CRC check in USB3.0 can hardly satisfy it. Thus, this paper mainly focuses on the USB3.0 data link layer data packet CRC validation. This paper is divided into two parts, theoretical analysis and design implement. The theoretical analysis part starts from USB3.0 protocol. It gives a brief introduction to protocol, data packets, data transmission types, etc. It focuses on the analysis of the function of USB3.0 link layer, link layer packet structure, link training and status of the state machine (LTSSM), etc. The design and implement part first analyses the CRC. Traditional CRC check in USB3.0 data link layer is serial. In order to improve the transmission speed, it is necessary to increase the clock frequency. The existing technological conditions limit the further improvement of the clock frequency. Thus it limits the USB3.0 data transmission speed. Then this part designs the CRC-16 in link layer packet header and the CRC-32 in link layer date packet date field. This part designs the CRC-32 in date field as serial, and concurrent look-up table design. The concurrent look-up table design CRC-32 occupies certain table space. Repeating table look-up reduces the computing speed. Based on the serial CRC-32 algorithm and the concurrent look-up table CRC-32 algorithm, this paper derives a new recursive concurrent CRC-32 algorithm. Compared with the existing look-up table concurrent CRC-32 algorithm, this new algorithm saves the space of storing the remainder list, improves the speed of operation. Finally, this part uses Verilog to realize the algorithm. |
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