Design And Verification Of USB3.0 Physical Layer Digital Module

As a standard transmission interface, USB (Universal Serial Bus) is widely used in recent years. Since the first USB3.0 standard specification released in November 2008, many foreign manufacturers rapidly provide solutions. With strong support of manufacturers, the USB3.0 device occupies a very important position in a portable flash memory and high-speed data transmission, showing a competitive edge; But in the country, there are few independent intellectual property rights with USB3.0 solutions. Therefore, the design and realization of autonomous USB3.0 chip has practical significance. Compared with the previous versions of the USB specification, the performance of USB3.0 has been significantly improved:transfer rate up to 5Gbps, which increased 10 times over the previous generation. High performance and low power consumption is the mainstream ideology of modern IC design. How to achieve the balance between performance and power consumption in the USB3.0 circuit design is the key and difficult point that the designers must face.The physical layer is located in the bottom of USB3.0 hardware architecture. The transmission circuit can perform scrambling, coding and serializing in parallel, then serial output signal; receiving circuit can extract clock from serial signal. Processed by deserialization, frame synchronization and elastic buffer circuit, a steady data stream arrived. After decoding and descrambling, signal is recovered to parallel data and sent to the link layer. In this paper, with the requirements of USB3.0 specification, through research and analysis on characteristics of the physical layer, digital part was designed; besides, the circuit of link training, loop control and Bit Error Rate Test (BERT) were designed and verified.In this paper, the standard logic cell library of 40nm SMIC technology was used, and the Design Complier (DC) synthesis showed that citcuit can work stably in the 500MHz, which fulfilled the design requirements. The main work of this paper includes the following three parts:(1) On the basis of the USB3.0 specification study, the structure and design parameters of physical layer were analyzed and the plan of the overall structure was realized, According to the function of the circuit, the digital part was divided into four parts, the transmission channel, the receiving channel, the channel management and the link training;(2) Using the idea of modular circuit design, the RTL (Register Transfer Level) level function of the digital part circuit was described in Verilog language; The working principle and design scheme of the key circuit were introduced in detail. Meanwhile, the paper put forward an effective solution to the difficult problems in design;(3) ModelSim was used to simulate the function of digital part circuit; The VC709 Connectivity Kit was chosed to build a hardware test platform and used for board level verification. In order to improve the flexibility of test data, the structure of host computer and slave computer was used:the software in host computer control built-in microcontroller by serial port. This structure realized the data interaction between computer and FPGA, which is convenient to verify the error free transmission test of the digital part circuit.