Research On Real-time Simulation Of RISC-V Instruction System Based On Shenwei CPU

With the continuous development of computer architecture,various instruction set architectures have been continuously proposed,such as Intel X86 architecture and ARM company's ARM architecture,which are now mainstream processor architectures and are in a monopoly position in the market.In order to break their monopoly,professors at the University of California,Berkeley designed the open source RISC-V instruction architecture,which has received widespread attention from the international community.The design of domestic CPUs has developed rapidly in recent years,among which Shenwei instruction set architecture is a relatively mature instruction set architecture in China.In order to broaden the ecological environment of Shenwei instruction set architecture processors and promote the development of domestic processors,this article studies how to dynamically run the source code of RSIC-V on Shenwei processors.The main innovation of this article is to compare and analyze the most popular RISC-V instruction set architecture and the domestic independent instruction set architecture-Shenwei instruction set architecture,and study the similarities and differences between the two.Adopt dynamic binary translation technology to design a translation software to realize the simple/typical program of RISC-V instruction system running on the CPU based on Shenwei's independent instruction system in real time.The main work of this article is as follows:1.In-depth study of the RISC-V instruction set architecture and the Shenwei instruction set architecture,and an overall comparison of the two instruction set architectures in terms of processors,basic instructions,registers,and storage management mechanisms.Then the instruction format was compared in detail,and it was found that both used 32-bit fixed-length instruction encoding,and the opcode,register field,and operand field were in fixed positions.However,the encoding length and storage location of specific fields are different,and Shenwei supports up to four operands,while RISC-V supports up to three operands.Finally,the general register settings are also compared in detail,and it is found that both have 32 general integer registers,and both have constant zero registers,but the specific register codes are different.2.Using dynamic binary translation technology to design a translation software,and completed the coding and functional debugging of the translation software.The translation software receives the source program through the interface module and then performs data processing to determine the address and instruction code.Then the address is mapped and the instruction code is translated by the translation module.Address mapping uses dynamic maintenance of a Hash table to complete the one-toone mapping of the address of the RISC-V source program to the address of the executable program of the Shenwei platform.Instruction code translation identifies and identifies specific operation instructions and operands by classification,and then maps to Shenwei specific instructions to implement instruction translation.3.Write incentives and complete translation software testing.The experiment is divided into two parts.The first is to complete the translation test of RISC-V basic instructions to Shenwei instructions one by one.Then there are some simple and typical program tests.Test incentives for individual commands are developed by repeating the operation of individual commands.For simple and typical programs,test incentives(binary executable files)are obtained through C program compilation and execution.Analyze the experimental data and verify the feasibility and correctness of the dynamic translation of the RISC-V instruction set architecture to the Shenwei instruction set architecture.Finally,a simple analysis of the code expansion in the translation process,found that the translation process will lead to code expansion,affecting translation efficiency.