Extension And Implementation Of CNN Vector Instruction Set Based On RISC-V Architecture

More stricter requirements have been put on the real-time processing of massive data in the era of artificial intelligence.Due to the physical characteristics of integrated circuit transistors approaching their limits,it is difficult for traditional general-purpose processors to meet the requirements.In recent years,a wave of research on dedicated neural network accelerators has gradually arisen in order to make up for the shortcomings of general-purpose processors.This thesis designs a convolutional neural network accelerator and expands the vector instruction set of convolutional neural network based on the RISC-V architecture.The accelerator is embeded into Ridecore which is the open processor of RISC-V in order to test the performance of the neural network accelerator.Also,Ridecore is designed by the RISC-V instruction set architecture and is a two-way superscalar out-of-order processor.So far,the RISC-V organization has only defined the symbolic form of commonly used vector instruction sets,and does not create binary-coded vector instruction sets.In order to make the designed instruction set have a certain useful value,the instruction set in this paper combines the overall coding style of RISC-V instruction set and some features of MIPS SIMD vector instruction set.The neural network vector instruction set include convolution operation instructions,pooling operation instructions,and non-linear operation instructions.This thesis uses the Design Compile tool to comprehensively analyze the accelerator under the 28 nm process.The experimental results show that the accelerator unit can support a maximum frequency of 1.43 GHz.In terms of resource usage,the accelerator needs 4447 lookup tables and 277 register resources.After using the neural network accelerator,the maximum performance of the Ridecore processor can be increased by 212.9 times.