Implementation Of RISC-V Atomic Operation Instruction Based On Shenwei Architecture

With the continuous development of IC technology,the design of domestic processors has received extensive attention.However,the current instruction set architecture has problems such as intellectual property risks and high licensing fees,which severely limit the development of domestic processors.RISC-V(RISC-V Instruction Set Architecture)is a brand-new instruction set architecture released in recent years.It has the characteristics of simplicity and open source.Its atomic operation instructions are mostly used to solve the concurrent and competitive risks of processors.Therefore,atomic operation has always been one of the key research objects of processors.Shenwei is an early mature independent research and development brand in China and occupies an important position in domestic processors.Therefore,the implementatio n of RISC-V atomic operating instructions based on Shenwei architecture has played a positive and important role in the development of domestic processors.Firstly,this paper introduces the mainstream trend of processor multi-core architecture due to Moore's Law's gradual failure.In multi-core architecture,processor concurrency and competitive risk will inevitably occur.The "lock mechanism" implemented on the basis of atomic operation instructions is one of the effective methods to solve this problem,and four kinds of commonly used lock mechanisms are listed respectively to illustrate it.Then,taking ARM,x86 and RISC-V architectures as examples,the implementation principle and application background of atomic operation instructions are analyzed.RISC-V atomic operation instructions have the characteristics of diversity and high efficiency,so the implementation of RISC-V atomic operation instructions has become a research hotspot.After that,it introduces the basic knowledge of RISC-V and Shenwei instruction sets,including instruction format and instruction type,and the unique modular organization form of RISC-V.This paper compares the atomic operating instructions of Shenwei and RISC-V architectures to develop a design method for RISC-V atomic operating instructions based on Shenwei architecture.Based on the consideration of different design directions,this paper proposes two implementation methods: First,based on the consideration of complexity,according to the different functions of RISC-V atomic operation instructions and based on the characteristics of Shenwei processor core,necessary hardware logic circuits are added to implement each instruction function concretely.Second,based on timing path considerations: RISC-V atomic operation instructions are split into two basic instructions of the Shenwei processor core using instruction splitting technology.The functions realized by a single RISC-V atomic operation instruction are implemented by the two instructions in turn.In the process of system implementation,pipeline conflicts need to be faced.Based on the traditional five-stage pipeline and Shenwei superscalar pipeline structures,this paper proposes a solution.After that,according to the above two design methods,the module design is carried out respectively,and the specific structure of the design module and the implementation process of the instructions are described in detail.In this paper,the main modules are finger fetching,transmitting and memory accessing,among which the memory data conflicts generated in the memory accessing control module are studied and classified and corresponding solutions are found.In the end,this paper builds a verification environment to simulate and verify each module.The experimental results show that the two design schemes proposed in this paper can be implemented,and the atomic operation instructions designed and implemented by considering the timing path is shortened by 20%,and finally the locking and unlocking efficiency of RISC-V lock instructions is improved by 40% compared with Shenwei architecture.