Dynamic Optimization And Microprocessor Architecture Support For Dynamic Binary Translation

30s' development, microprocessor has spreaded into every space of community and everyday life. This mature and successful industry focuses on several monopolistic architecture. To catch up with the endless needs, new microprocessor should be faster, more efficient and in novel architecture. But in order to protect previous investment in software, new microprocessor has to keep the binary code compatibility with traditional architecture and application. Today, binary compatibility is the key feature to decide whether a microprocessor can survive in the market, and also it becomes the major obstacle for the creative design.Combining dynamic binary translation with microachitecture design is an emerging way to keep the performance improving and free the use of new technology in architecture. The software of dynamic binary translation will substitute complex hardware logic for compatibility. The execution engine will be simplified and easy to achieve high frequency. Dynamic optimization will improve the whole performance. It provides a novel way to design microprocessor and lowers the demands on microelectronics manufatcure.The dissertation focuses on the dyanmic optimization and the microarchitecture support for binary translation microprocessor. Based on the novel model of scalable processor, the dissertation proposes an adaptive low-cost profiling technology, a new optimizing algorithm and the framework of multi-level opitimization. This dissertation provides the design of key hardware components and main software algorithm for binary translation microprocessor. The main contributions are as follows:1. The dissertation thoroughly investigates the present researches on microprocessor architecture and dynamic binary translation. Several important projects and products are analyzed. After summarizing their strongpoint and shortpoint, our conclusion is that complete com-patiblity, high performance and unlimited hardware design is the object of binary translation processor.2. As the base of design, the dissertation proposes a binary translation processor model named Transtar-VISA. It's a scalable microarchitecture framework based on binary translation and optimization. A new VLIW processing element, Transtar-Core, is introduced to investigate the efficiency and effect of Transtar-VISA in various scenes, including the partial architectural evolution, the migration from IA-32 to VLIW and the simultaneous support of multi-ISA by a single execution core.3. The discovery of hot code is the first step of translation and optimization. A new hardware profiler named CSP has been proposed to find the hot path in runtime. CSP will not increase the execution time for profiling. Reasonable hardware cost will get precise profile. The translator and optimizer can adjust CSP to collect the information of desired path.