Research And Design Of Multiplier-Accumulator Uint Based On RISC-V Instruction Set Microprocessor

RISC-V architecture with the characteristics of configurable and extensible instruction set is a new,completely open source instruction set architecture,which has attracted wide attention from the big IC companies and the universities.The high-performance microprocessors or low-power microprocessors can be designed with RISC-V architecture according to the users' needs.In recent years,research of the RISC-V instruction set microprocessor has become more and more popular.There are increasing demands on the data computing and processing capabilities of the microprocessors in the fields of the Internet of Things,artificial intelligence and big data.The multiplication instructions and addition instructions are executed separately in existing general-purpose microprocessors,which makes them inefficient for multiple multiplication and addition operations.The multiplication and addition instructions can be combined into a Multiply Accumulate instruction to perform both multiplication and addition operations.The scheme of the general RISC-V instruction set microprocessor+hardware acceleration unit are realized to improve the calculation and processing power of the microprocessor by the designed Multiply Add unit performing the multiplication and addition operations.In this paper,the instruction types,coding rules and third-party instruction expansion rules of RISC-V instruction set architecture,and the structure and performance of different adder and multiplier were analyzed.Four integer Multiply Accumulate instructions based on RISC-V architecture are extended.The Multiply Add unit of the RISC-V instruction set that supports 32-bit signed and unsigned multiplication and multiplication operations was designed.The partial product compression module is composed of an improved 5-2 compressor and a 4-2 compressor.The addition operand of the multiplication and addition instruction is compressed as a partial product in the partial product compression module,which reduces the delay time of the partial product compression module.The final addition module is composed of a 64-bit trapezoidal grouping structure based on the carry selective adder structure,which avoids the extra waiting time of the final addition module.Based on the open source Hummingbird E203 processor in RISC-V instruction set microprocessor,the fetch function module,the decoding function module,the execution function module and the write back function module of the multiplication and addition instruction were designed.The Hummingbird E203 processor was improved,and the design of multiplication and addition unit was realized based on RISC-V instruction set microprocessor.The logic simulation of the Multiply Add unit designed with the Verilog hardware description language was done by the VCS tool.Based on the 180nm process,the logic synthesis of the Multiply Add unit was completed by the DC tool under the typical condition.The layout design of the multiplication and addition unit was designed by ICC tool,and the GDSII file was generated.The clock frequency was up to 100MHz,the area was 116485.57um2,and the power consumption was 37.26mW.Based on the self-test trial cases provided officially by the RISC-V and the hummingbirds E203 processor test platform,the functions of the fetch unit and perform/write back of the improved hummingbird E203 processor were simulated.The functions of the improved hummingbird E203 processor were validated correctly.The extended Multiply Accumulate instructions was executed in the improved the hummingbird E203 a processor,and the functions of the Multiply Add unit were validated correctly.The effect of the multiplication and addition operation was compared in the improved Hummingbird E203 processor for the Multiply Accumulate instructions,the multiplication instructions and the addition instructions by simulation.The simulation results show that the multiplication and addition operation is significantly accelerated by the combination scheme of the Multiply Add unit and the Multiply Accumulate instructions,which is 33%higher than the scheme of the Multiply Add unit without the Multiply Accumulate instructions,and is 88.2%higher than the scheme of the without the Multiply Add unit and the Multiply Accumulate instructions.